JPS6320845A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6320845A
JPS6320845A JP61165925A JP16592586A JPS6320845A JP S6320845 A JPS6320845 A JP S6320845A JP 61165925 A JP61165925 A JP 61165925A JP 16592586 A JP16592586 A JP 16592586A JP S6320845 A JPS6320845 A JP S6320845A
Authority
JP
Japan
Prior art keywords
conductive
insulated film
film
conductive materials
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61165925A
Other languages
Japanese (ja)
Inventor
Takayuki Kurayama
倉山　隆之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP61165925A priority Critical patent/JPS6320845A/en
Publication of JPS6320845A publication Critical patent/JPS6320845A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid developing corrosion and crack of conductive films and prevent electrical short-circuit troubles of conductive materials from coming about by preparing the first insulated film that is provided by covering a semiconductor substrate together with peripheral parts of conductive films as well as the second insulated film that is provided by covering the conductive materials, the conductive films, and the first insulated film. CONSTITUTION:The first insulated film 5 is formed at all the surface of semiconductor substrate 3 with the exception of areas where conductive films 4 for external connections formed on the substrate 3 are connected to conductive materials 6 for the external connections. The conductive films 4 are connected to case leads 1 through conductive materials 6 and the second insulated film 7 is formed so as to cover the case leads 1, conductive materials 6 as well as insulated film 5. Processes other than a process forming the insurated film 7 are well-known methods and the process forming insulated film 7 is attained by performing vacuum vaporization, spatter, and CVD processes end the like. Thus, the insulated film avoids developing corrosion and crack of the conductive films 4 and prevents the conductive materials 6 from being short-circuited.

Description

【発明の詳細な説明】 〔産業上の利用分野：１ 本発明は半導体集積回路に関する。[Detailed description of the invention] [Industrial application field: 1 The present invention relates to semiconductor integrated circuits.

［従来の技術゛１ 従来の半導体集積回路は、第３図及び第４図に示すよう
に、半導体基板３上は外部接続用の導電膜４の周辺部を
含めて第１の絶縁膜５で寵われているが、導電膜４とケ
ースリード１及び外部接続用の導電材６は、剥出しの状
態となっていた。[Prior Art 1] As shown in FIGS. 3 and 4, in a conventional semiconductor integrated circuit, a first insulating film 5 is formed on a semiconductor substrate 3 including a peripheral part of a conductive film 4 for external connection. Although preferred, the conductive film 4, case lead 1, and conductive material 6 for external connection were exposed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体集積回路は、導電股上は第１の絶
縁膜で覆われておらず、そこから製造過程の外気中に含
まれる水蒸気の浸入などにより、アルミニウムの導電膜
を腐食させ回路機能に障害を発生ずるという第１の欠点
がある。In the conventional semiconductor integrated circuit described above, the conductive layer is not covered with the first insulating film, and water vapor contained in the outside air during the manufacturing process corrodes the aluminum conductive film and impairs the circuit function. The first drawback is that it causes trouble.

又、樹脂を封入する場合に、樹脂封入時の機械的圧力に
より、外部接続用の導電材同士の接触、あるいは、導電
材とケースリードとの接触、あるいは、導電材と半導体
基板との接触により、電気的短絡を引起こすという第２
の欠点がある。In addition, when encapsulating resin, mechanical pressure during resin encapsulation may cause contact between conductive materials for external connections, contact between conductive materials and case leads, or contact between conductive materials and semiconductor substrate. , the second is that it causes an electrical short circuit.
There are drawbacks.

更に、封入樹脂の熱′Ｊ５ｊ張により、半導体基板表面
に圧力が加わり、鳴積回路−Ｌの導電膜にひび割れ等の
欠陥を生じるという第３の欠点がある。Furthermore, there is a third drawback that pressure is applied to the surface of the semiconductor substrate due to the heat expansion of the encapsulating resin, causing defects such as cracks in the conductive film of the multilayer circuit-L.

本発明の目的は、導電膜の１ｇ食及びひび割れを発生せ
ずかつ導電材の′Ｉ′Ｉｉ路を防止て′きる半導体集積
回路を提供することにある 〔問題点を解決するための手段〕 本発明の半導体集積回路は、半導体基板の周辺に設けら
れた外部接続用の導電膜と、該導電膜のほぼ中央に機械
的に接続された導電材と、前記導電膜の周辺部をかみ前
記半導体基板を覆って設けられた第１の絶縁膜と、前記
導電材と前記導電膜と前記第１の絶縁膜を覆って設けら
れた第２の絶縁膜とを有している。An object of the present invention is to provide a semiconductor integrated circuit that does not cause 1g corrosion or cracking of the conductive film and can prevent 'I'Ii' paths of the conductive material. [Means for solving the problems] The semiconductor integrated circuit of the present invention includes a conductive film for external connection provided around the periphery of a semiconductor substrate, a conductive material mechanically connected to approximately the center of the conductive film, and a conductive material that engages the periphery of the conductive film. The semiconductor device includes a first insulating film provided to cover a semiconductor substrate, and a second insulating film provided to cover the conductive material, the conductive film, and the first insulating film.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例の斜視図、第２図は第１図の
Ａ−Ａ′線断面図である。FIG. 1 is a perspective view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line A-A' in FIG.

第１図及び第２図に示すように、本実施例は公知のチ・
ツブ製造方法で半導体基板３上に形成された外部接続用
の導電膜４の外部接続用の導電材６を接続する領域を除
く半導体基板３の全面に公知のチップ製造方法で第１の
絶縁膜５を形成する。As shown in FIGS. 1 and 2, this embodiment uses a known chip.
A first insulating film is formed by a known chip manufacturing method on the entire surface of the semiconductor substrate 3 except for the area where the conductive material 6 for external connection is connected to the conductive film 4 for external connection formed on the semiconductor substrate 3 by the lump manufacturing method. form 5.

導電膜４とケースリード１は導電材６で公知の接続方法
で接続し、ケースリード１と導電材６と絶縁膜５を覆う
様に第２の絶縁膜７３形成している。The conductive film 4 and the case lead 1 are connected using a conductive material 6 using a known connection method, and a second insulating film 73 is formed to cover the case lead 1, the conductive material 6, and the insulating film 5.

製造工程としては、公知の方法で半導体基板３Ｆに集積
回路及び導電膜４を形成する第１の工程と、公知の方法
で絶縁膜５を形成する第２の工程と、公知の方法で機械
的に導電膜４とケースリード１を導電材６で接続する第
３の工程と、絶縁膜７を形成する第４の工程とからなる
。The manufacturing process includes a first step of forming an integrated circuit and a conductive film 4 on a semiconductor substrate 3F by a known method, a second step of forming an insulating film 5 by a known method, and a mechanical step of forming an insulating film 5 by a known method. The method consists of a third step of connecting the conductive film 4 and the case lead 1 with a conductive material 6, and a fourth step of forming the insulating film 7.

ここで、絶縁膜７を形成する第ｉｌの工程以外は公知の
方法であり、絶縁膜７を形成する第４の工程は真空蒸着
、スパッタ法及びＣＶＤ法等で達成できる。Here, steps other than the il-th step of forming the insulating film 7 are performed using known methods, and the fourth step of forming the insulating film 7 can be achieved by vacuum evaporation, sputtering, CVD, or the like.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明の半導体集積回路は、導電膜
の上部は第２の絶縁膜により覆われているので、外気中
の水蒸気の侵入による集積回路上のアルミニウムの導電
膜の腐食を防止できる効果がある。As explained above, in the semiconductor integrated circuit of the present invention, since the upper part of the conductive film is covered with the second insulating film, corrosion of the aluminum conductive film on the integrated circuit due to the intrusion of water vapor from the outside air can be prevented. effective.

又、導電材とケースリードと半導体基板を陰む全表面と
に第２の絶縁膜が形成されるので、パッケージ工程の樹
脂封入にさいしてのｎ　ｈＭ的正圧力より、導電材同士
、あるいは、導電材とケースリード、あるいは、導電材
と半導体基板とが接触しても電気的短絡障害の発生を防
止できるという効果がある。In addition, since the second insulating film is formed on the conductive material, the case lead, and the entire surface covering the semiconductor substrate, the conductive materials may be separated from each other or Even if the conductive material and the case lead or the conductive material and the semiconductor substrate come into contact, it is possible to prevent an electrical short circuit from occurring.

更に、樹脂の熱膨張による半導体基板への圧力ら第２の
絶縁膜により緩和されるので、集積回路トの導電膜のひ
び割れ等の欠陥が発生することを防止できるという効果
がある。Furthermore, since the second insulating film relieves pressure on the semiconductor substrate due to thermal expansion of the resin, it is possible to prevent defects such as cracks in the conductive film of the integrated circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の斜視図、第２図は第１図の
Ａ−Ａ′線断面図、第３図は従来の半導体集積回路の一
例の斜視図、第４図は第３図のＢ−Ｂ′線断面図である
。 １・・・ケースリード、２・・・チ・ツブアイランド、
３・・・半導体基板、４・・・導電膜、５・・絶縁膜、
６・・・導電材、７・・・絶縁膜。 ・ト］ １、ン１；Ω メ　　　　５，７托ル臘 ・Ａ ；ノ　　　　　　　系　２　凹FIG. 1 is a perspective view of an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 1, FIG. 3 is a perspective view of an example of a conventional semiconductor integrated circuit, and FIG. FIG. 4 is a sectional view taken along line BB' in FIG. 3; 1... Case lead, 2... Chi Tubu Island,
3... Semiconductor substrate, 4... Conductive film, 5... Insulating film,
6... Conductive material, 7... Insulating film.・G] 1, N1;Ω Me 5,7 托臘・A;ノ System 2 Concave

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の周辺に設けられた外部接続用の導電膜と、
該導電膜のほぼ中央に機械的に接続された導電材と、前
記導電膜の周辺部を含み前記半導体基板を覆って設けら
れた第１の絶縁膜と、前記導電材と前記導電膜と前記第
１の絶縁膜を覆つて設けられた第２の絶縁膜とを有する
半導体集積回路。A conductive film for external connection provided around the semiconductor substrate,
a conductive material mechanically connected to approximately the center of the conductive film; a first insulating film provided covering the semiconductor substrate including a peripheral portion of the conductive film; the conductive material, the conductive film, and the conductive film; A semiconductor integrated circuit having a second insulating film provided covering a first insulating film.
JP61165925A 1986-07-14 1986-07-14 Semiconductor integrated circuit Pending JPS6320845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61165925A JPS6320845A (en) 1986-07-14 1986-07-14 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61165925A JPS6320845A (en) 1986-07-14 1986-07-14 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6320845A true JPS6320845A (en) 1988-01-28

Family

ID=15821615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61165925A Pending JPS6320845A (en) 1986-07-14 1986-07-14 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6320845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145607A (en) * 1980-04-11 1981-11-12 Nippon Oil Co Ltd Wire or cable protection coating layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51136283A (en) * 1975-04-28 1976-11-25 Ncr Co Method and apparatus for protecting ultra small electronic devices
JPS5680151A (en) * 1979-12-05 1981-07-01 Seiichiro Sogo Production of semiconductor device having plated projecting electrode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51136283A (en) * 1975-04-28 1976-11-25 Ncr Co Method and apparatus for protecting ultra small electronic devices
JPS5680151A (en) * 1979-12-05 1981-07-01 Seiichiro Sogo Production of semiconductor device having plated projecting electrode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145607A (en) * 1980-04-11 1981-11-12 Nippon Oil Co Ltd Wire or cable protection coating layer
JPS6342363B2 (en) * 1980-04-11 1988-08-23 Nippon Oil Co Ltd

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