JPS6144452Y2 - - Google Patents

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Publication number
JPS6144452Y2
JPS6144452Y2 JP1980055566U JP5556680U JPS6144452Y2 JP S6144452 Y2 JPS6144452 Y2 JP S6144452Y2 JP 1980055566 U JP1980055566 U JP 1980055566U JP 5556680 U JP5556680 U JP 5556680U JP S6144452 Y2 JPS6144452 Y2 JP S6144452Y2
Authority
JP
Japan
Prior art keywords
bonding pad
semiconductor device
package
metal
grain size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980055566U
Other languages
Japanese (ja)
Other versions
JPS56157743U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Priority to JP1980055566U priority Critical patent/JPS6144452Y2/ja
Publication of JPS56157743U publication Critical patent/JPS56157743U/ja
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Publication of JPS6144452Y2 publication Critical patent/JPS6144452Y2/ja
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 本考案は、半導体集積回路チツプをパツケージ
内に組込む過程において、当該半導体集積回路チ
ツプ内に設けられたボンデイング・パツドと、前
記パツケージ内に設けられた電極とを、金属線を
用いて電気的に接続するボンデイング工程で生ず
る歩留りの低下を防止する新規な構造のボンデイ
ング・パツドに関するものである。[Detailed Description of the Invention] In the process of assembling a semiconductor integrated circuit chip into a package, the present invention connects bonding pads provided in the semiconductor integrated circuit chip and electrodes provided in the package to metal The present invention relates to a bonding pad with a novel structure that prevents a decrease in yield that occurs in a bonding process that uses wires for electrical connection.

ボンデイング・パツドは、半導体集積回路の出
力端子であり、該装置をパツケージに組込む過程
で、金属線を用いてパツケージ内に設けられた電
極と電気的に接続するべく半導体集積回路チツプ
（以下単に半導体装置という。）に設けられた電極
である。 A bonding pad is an output terminal of a semiconductor integrated circuit, and in the process of assembling the device into a package, it is used to electrically connect the bonding pad to an electrode provided in the package using metal wire. (referred to as the device).

第１図は、従来用いられている半導体装置にお
けるボンデイング・パツドの配置と、該半導体装
置を収めるパツケージの一部を示す概略平面図で
ある。図において、１は半導体装置を、２は該半
導体装置１内の回路が構成される領域を、３はボ
ンデイング・パツドとなる電極を、３２はボンデ
イング・パツド３と前記回路が構成される領域２
とを結ぶ配線パターンを、４は半導体装置１を収
めるパツケージの一部を、４５はパツケージ内に
設けられた電極を、５は該電極４５とボンデイン
グ・パツド３とを接続する金属線をそれぞれ示
す。半導体装置内の領域２で構成された回路は、
配線パターン３２を通じて、半導体装置の出力端
子であるボンデイング・パツド３に接続され、続
いて金属線５を通じてパツケージ内に設けられた
電極４５に接続される。 FIG. 1 is a schematic plan view showing the arrangement of bonding pads in a conventionally used semiconductor device and a part of a package that houses the semiconductor device. In the figure, 1 is a semiconductor device, 2 is a region in the semiconductor device 1 where a circuit is formed, 3 is an electrode that becomes a bonding pad, and 32 is a region 2 where a bonding pad 3 and the circuit are formed.
4 is a part of the package housing the semiconductor device 1, 45 is an electrode provided in the package, and 5 is a metal wire connecting the electrode 45 and the bonding pad 3. . The circuit configured in region 2 in the semiconductor device is
It is connected to a bonding pad 3, which is an output terminal of the semiconductor device, through a wiring pattern 32, and then connected to an electrode 45 provided inside the package through a metal wire 5.

第２図は、第１図におけるボンデイング・パツ
ド３の断面構造を説明する半導体装置およびパツ
ケージの一部を含む概略断面図であり、１５は半
導体基体を、１６は該半導体基体表面に設けられ
た絶縁膜を、３はボンデイング・パツドとなる金
属電極を、３２は金属配線パターンを、４はパツ
ケージの一部を、４５および４６はパツケージ内
に設けられた金属電極を、５はボンデイング・パ
ツド３とパツケージ内の電極４５とを結ぶ金属線
を、それぞれ示す。 FIG. 2 is a schematic cross-sectional view including a part of the semiconductor device and package, explaining the cross-sectional structure of the bonding pad 3 in FIG. 3 is a metal electrode that becomes a bonding pad, 32 is a metal wiring pattern, 4 is a part of the package, 45 and 46 are metal electrodes provided in the package, and 5 is a bonding pad 3. The metal wires connecting the electrode 45 and the electrode 45 in the package are respectively shown.

ボンデイング・パツド３と配線パターン３２は
通常は同一金属材料を用いて１回のフオトエツチ
ング工程で形成される。金属線５は、半導体基体
１５をパツケージ内に設けられた電極４６上に接
着せしめた後に、設けられる。 Bonding pad 3 and wiring pattern 32 are usually formed using the same metal material in one photoetching process. The metal wire 5 is provided after the semiconductor body 15 has been glued onto the electrode 46 provided within the package.

現在、半導体装置内に設けられるボンデイング
パツド３、配線パターン３２および回路構成領域
２の金属配線パターンはアルミニウムを用いて形
成される例が多い。アルミニウムは安価で、膜形
成および加工が容易である特徴を有しており優れ
た材料と言える。 At present, the bonding pad 3, the wiring pattern 32, and the metal wiring pattern of the circuit configuration region 2 provided in a semiconductor device are often formed using aluminum. Aluminum is inexpensive and can be easily formed and processed, making it an excellent material.

近年の半導体装置の高集積化に伴ない、１μｍ
程度の微細なパターンを精度良く形成することが
要求される。金属パターンを形成するアルミニウ
ム膜においては、かかる目的を達成するためにア
ルミニウム膜を構成する結晶粒径を１μｍ以下と
微細にする必要がある。アルミニウム膜の形成法
としては、例えば真空蒸着法が広く用いられてお
りこの場合結晶粒径の小さな膜を形成するには、
半導体基体温度の低い条件で真空蒸着を行えば良
い。かかる手段で、結晶粒径が0.2〜0.4μｍ程度
のアルミニウム膜が再現性良く形成できる。 With the recent increase in the integration of semiconductor devices, 1 μm
It is required to form extremely fine patterns with high precision. In order to achieve this objective in an aluminum film forming a metal pattern, it is necessary to make the crystal grain size of the aluminum film as fine as 1 μm or less. As a method for forming an aluminum film, for example, vacuum evaporation is widely used. In this case, in order to form a film with small crystal grain size,
Vacuum deposition may be performed under conditions where the semiconductor substrate temperature is low. By this means, an aluminum film having a crystal grain size of about 0.2 to 0.4 μm can be formed with good reproducibility.

しかしながら、かかる微細な結晶粒径からなる
アルミニウム膜を用いて半導体装置を形成した場
合、額装置をパツケージ内に組込む過程で歩留り
が著しく低下することが明らかとなつた。この原
因は、微結晶粒径アルミニウム膜の機械的強度が
著しく弱いためであると判明した。即ち、半導体
装置内に設けられたボンデイング・パツドとパツ
ケージ内に設けられた電極とを接続すべく、該ボ
ンデイング・パツドに金属線をボンデイングする
際に、半導体装置表面を破損し易いこと、また、
アルミニウム電極と金属線との固着強度が弱く、
線が取れ易いことによる。 However, it has become clear that when a semiconductor device is formed using an aluminum film having such a fine crystal grain size, the yield is significantly reduced during the process of assembling the forehead device into a package. The reason for this was found to be that the mechanical strength of the microcrystalline aluminum film was extremely weak. That is, when bonding a metal wire to a bonding pad provided in a semiconductor device and an electrode provided in a package in order to connect the bonding pad provided in the package, the surface of the semiconductor device is likely to be damaged;
The adhesion strength between the aluminum electrode and the metal wire is weak,
This is because the lines are easy to remove.

かかる歩留りの低下を防止する方法の１つは、
アルミニウム膜を厚くすることであるが、例えば
２μｍ厚としても機械的強度は大幅には改善され
ない上に、微細電極パターンの形成が困難とな
る。また、他の方法は、真空蒸着を半導体基体温
度の高い条件で行い、アルミニウム膜の結晶粒径
を２〜３μｍ程度に大きくすれば解決されるが、
一方微細な精度の良い電極パターンの形成は困難
となる。 One of the ways to prevent such a decrease in yield is to
Although the aluminum film should be made thicker, for example, even if the thickness is 2 μm, the mechanical strength will not be significantly improved, and it will be difficult to form a fine electrode pattern. In addition, other methods can be solved by performing vacuum evaporation under conditions where the semiconductor substrate temperature is high and increasing the crystal grain size of the aluminum film to about 2 to 3 μm.
On the other hand, it becomes difficult to form fine and precise electrode patterns.

本考案は、上記した微細結晶粒アルミニウム膜
における欠点を改善する手段を具備したボンデイ
ング・パツドに関するものであり、その要旨は、
ボンデイング・パツドを構成する領域の金属膜の
結晶粒径が少くとも１μｍ以上と大きな結晶粒径
をもつていることにある。 The present invention relates to a bonding pad equipped with means for improving the above-mentioned defects in the fine-grained aluminum film, and its gist is as follows:
The metal film in the region constituting the bonding pad has a large crystal grain size of at least 1 μm or more.

以下、本考案になるボンデイング・パツドにつ
いてその形成法の一例に触れながら図を用いて説
明する。 Hereinafter, the bonding pad according to the present invention will be explained using the drawings while referring to an example of its formation method.

第３図は、本考案になるボンデイング・パツド
を設けた半導体装置の断面構造を示す図であり、
第２図と同記号は同種の物であることを示す。 FIG. 3 is a diagram showing a cross-sectional structure of a semiconductor device provided with a bonding pad according to the present invention.
The same symbols as in Figure 2 indicate the same type of item.

第３図において、３５はボンデイング・パツド
の全領域を構成する大きな結晶粒径を有する金属
膜を、３２は該金属膜３５と前記回路構成領域
（第１図の２）とを接続するべく設けられた小さ
な結晶粒径を有する配線用金属膜をそれぞれ示
す。かかる構造のボンデイング・パツドを含む半
導体装置は、例えば半導体基体温度50〜100℃の
条件での真空蒸着等の手段により、結晶粒径0.2
〜0.4μｍ、膜厚0.5〜１μｍのアルミニウム膜を
設けた後に、ボンデイング・パツド領域３５、配
線パターン３２および半導体装置内の回路が構成
される領域（第１図の２）の金属配線パターンを
１回のフオトエツチング工程を経て形成し、しか
る後にボンデイング・パツド領域３５のみに例え
ばレーザー光を照射することにより形成できる。
即ち、レーザー光はボンデイング・パツド領域の
アルミニウム膜３５の結晶粒径を大きくするべく
用いられているものであり、当該結晶粒径を１〜
３μｍ程度にすれば充分であることから、アルミ
ニウム膜３５を溶融させるほど大きなエネルギー
は必要でない。好ましい一例は、CW発振型YAG
レーザで105W／cm2程度の光を照射することであ
る。レーザー光は、ボンデイング・パツド領域を
含め半導体装置（第１図の１）の表面全域に照射
することはもちろん可能である。しかし、回路が
構成される領域（第１図の２）内の金属膜の結晶
粒径はむしろ微細であることが望ましいことか
ら、レーザー光照射はボンデイング・パツド部分
３５にのみ選択的に行う方が望ましく、そうする
ことでより良好な結果を得た。また、ボンデイン
グ・パツドは、半導体装置を構成するチツプの周
辺部分に配列されることが多いことから、光を遮
断するマスクを用いて回路構成領域（第１図の
２）にはレーザー光が照射されないようにするこ
とでも本考案の目的が達成できる。さらに100μ
ｍ径程度のレーザー光スポツトをボンデイング・
パツド部分に順次照射することでも良い結果を得
る。 In FIG. 3, reference numeral 35 denotes a metal film having a large crystal grain size constituting the entire area of the bonding pad, and 32 is provided to connect the metal film 35 and the circuit configuration area (2 in FIG. 1). Each of the wiring metal films having a small crystal grain size is shown. A semiconductor device including a bonding pad having such a structure can be manufactured with a crystal grain size of 0.2 by means such as vacuum evaporation at a semiconductor substrate temperature of 50 to 100°C.
After forming an aluminum film with a thickness of ~0.4 μm and a film thickness of 0.5 to 1 μm, the bonding pad region 35, the wiring pattern 32, and the metal wiring pattern in the region (2 in FIG. 1) where the circuit in the semiconductor device is constructed are The bonding pad region 35 can be formed by performing multiple photo-etching steps, and then by irradiating only the bonding pad region 35 with, for example, a laser beam.
That is, the laser beam is used to increase the crystal grain size of the aluminum film 35 in the bonding pad region, and the crystal grain size is increased from 1 to 1.
Since a thickness of about 3 μm is sufficient, energy large enough to melt the aluminum film 35 is not required. A preferable example is CW oscillation type YAG
It involves irradiating light of approximately 10 5 W/cm 2 with a laser. It is of course possible to irradiate the entire surface of the semiconductor device (1 in FIG. 1) with laser light, including the bonding pad area. However, since it is preferable that the crystal grain size of the metal film in the area where the circuit is configured (2 in Figure 1) be fine, it is preferable to irradiate the laser beam selectively only to the bonding pad portion 35. is desirable, and we obtained better results by doing so. In addition, bonding pads are often arranged in the periphery of a chip that constitutes a semiconductor device, so a mask that blocks light is used to irradiate the circuit configuration area (2 in Figure 1) with laser light. The purpose of the present invention can also be achieved by preventing this from occurring. Another 100μ
Bonding a laser beam spot with a diameter of about m
Good results can also be obtained by sequentially irradiating the pad areas.

上記したレーザー光照射は、複数の半導体装置
が設けられたウエハー状態で行えるのはもちろん
可能であるが、半導体装置をチツプに分離しパツ
ケージ上に接着せしめた後に行うのも一方法であ
る。かかる方法は、ボンデイング装置にレーザー
光スポツト照射装置を組み込み、ボンデイング・
パツド領域にレーザー光を照射すると共にボンデ
イングを行うことが出来、好ましい方法である。 It is of course possible to perform the above-mentioned laser beam irradiation on a wafer on which a plurality of semiconductor devices are provided, but it is also possible to perform the laser beam irradiation after separating the semiconductor devices into chips and bonding them onto a package. This method incorporates a laser beam spot irradiation device into the bonding device and performs bonding and
This is a preferred method because bonding can be performed while irradiating the pad area with laser light.

以上、金属膜にアルミニウムを用いた例につい
て本考案を説明したが、本考案は他の金属膜に適
用できることは明らかである。また、ボンデイン
グ・パツド領域の金属膜の結晶粒径を増加する手
段としてレーザー光を用いたが、電子ビーム、フ
ラツシユランプさらには太陽光線等を用いても本
考案の目的は達成できる。 Although the present invention has been described above with respect to an example in which aluminum is used as the metal film, it is clear that the present invention can be applied to other metal films. Further, although laser light was used as a means of increasing the crystal grain size of the metal film in the bonding pad region, the object of the present invention can also be achieved by using an electron beam, a flash lamp, or even sunlight.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は半導体装置におけるボンデイング・パ
ツドの配置と、該半導体装置をパツケージに収め
た様子を説明する概略平面図であり、第２図は従
来ボンデイング・パツドの構造を説明する半導体
装置およびパツケージの一部を含む概略断面図で
あり、第３図は本考案のボンデイング・パツドを
設けた半導体装置の構造を説明する概略断面図で
ある。図において、１は半導体装置を、１５は半
導体基体を、１６は絶縁膜を、２は半導体装置１
内の回路が構成される領域を３，３５はボンデイ
ング・パツドとなる金属電極を、３２は金属配線
パターンを、４は半導体装置１を収めるパツケー
ジの一部を、４５，４６はパツケージ内に設けら
れた電極を、５は金属線をそれぞれ示す。 FIG. 1 is a schematic plan view illustrating the arrangement of bonding pads in a semiconductor device and how the semiconductor device is housed in a package. FIG. 2 is a schematic plan view of a semiconductor device and package illustrating the structure of a conventional bonding pad. FIG. 3 is a schematic cross-sectional view including a portion of the semiconductor device, and FIG. 3 is a schematic cross-sectional view illustrating the structure of a semiconductor device provided with the bonding pad of the present invention. In the figure, 1 is a semiconductor device, 15 is a semiconductor substrate, 16 is an insulating film, and 2 is a semiconductor device 1.
3 and 35 are metal electrodes serving as bonding pads, 32 is a metal wiring pattern, 4 is a part of the package that houses the semiconductor device 1, and 45 and 46 are provided inside the package. 5 indicates a metal wire, and 5 indicates a metal wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路の表面に設けられ、当該回路外
部と電気接続する金属線の接続に供するボンデイ
ング・パツド領域において、ボンデイング・パツ
ド領域を構成する金属膜の結晶粒径がそれ以外の
領域の配線用金属膜の結晶粒径より大きく形成さ
れることを特徴とした半導体集積回路のボンデイ
ング・パツド。 In a bonding pad region provided on the surface of a semiconductor integrated circuit and used for connecting metal wires for electrical connection to the outside of the circuit, the crystal grain size of the metal film constituting the bonding pad region is the same as that of wiring metal in other regions. A bonding pad for semiconductor integrated circuits characterized by being formed larger than the crystal grain size of the film.
JP1980055566U 1980-04-23 1980-04-23 Expired JPS6144452Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980055566U JPS6144452Y2 (en) 1980-04-23 1980-04-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980055566U JPS6144452Y2 (en) 1980-04-23 1980-04-23

Publications (2)

Publication Number Publication Date
JPS56157743U JPS56157743U (en) 1981-11-25
JPS6144452Y2 true JPS6144452Y2 (en) 1986-12-15

Family

ID=29650218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980055566U Expired JPS6144452Y2 (en) 1980-04-23 1980-04-23

Country Status (1)

Country Link
JP (1) JPS6144452Y2 (en)

Also Published As

Publication number Publication date
JPS56157743U (en) 1981-11-25

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