JPS63202147A - Parity counting method - Google Patents

Abstract

PURPOSE:To make the circuit constitution not complicated even when the unit of parity bit addition is increased by applying clock input of a flip-flop while it is switched for two systems with a data input alternately thereby counting the parity sequentially with respect to a unit data. CONSTITUTION:A comparison pulse (e) is outputted from a half clock delay circuit 7 after the 18th pulse of a read clock (b) and inputted to flip-flops 13, 14. Thus, the result of comparison between the data parity bit and the parity counted from a hexadecimal data '1A(h)' by the said comparison pulse (e) is stored in an output Q of the flip-flop 13. Similarly, the result of comparison between the parity counted from a hexadecimal data '2B(h)' and the parity bit of the said data is stored in an output Q of the flip-flop 14. When the output of the result of comparison is '0(2)', no error exists in the input data and when the output is '1(2)', the presence of an error in the input data is discriminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for counting the parity of a digital signal.

[Prior art and its problems] In data transmission using digital signals, as a method of determining whether the transmitted data is correct, the transmitting side adds parity pits to each 8-bit unit or 16-bit unit of data, for example. A common method is to count the parity of the received data on the receiving side, compare the counting result with the received parity bit, and determine that the received data is correct if the two match.

FIG. 4 is a block diagram showing the main parts of a circuit conventionally used on the receiving side for such determination.
5 is a pulse diagram for explaining the operation of the circuit, and the operation will be explained below with reference to this figure and FIG. 4.

S5 (a) shows an example of input data a.

The data is rlA (h)J r2B(h
)" when transmitting 2 bytes of data, and a 1-bit rl is used as a start bit before the data.
(2)'' and the above-mentioned parity bit for each byte is added after the above-mentioned data. The parity is odd parity, and the parity pit of "IA (h)J is ro
(2)'' and the parity pit of r2B (h)J is ``1(2)''.

FIG. 5(b) is an example of the read clock 5 input in synchronization with the input data.

As shown in FIG. 4, the input data a and read clock b are input to the start bit detection circuit 3. When the detection circuit detects the start bit of input data a, it outputs a rear pulse C as shown in FIG. 5(C).

As shown in FIG. 4, the clearing pulse C is input to a divide-by-8 circuit 4 and a divide-by-18 circuit 5.

A read clock b is input to these circuits, and when the clear pulse C is input, the pulses of the read clock b are counted. The divide-by-8 circuit 4 outputs one pulse for every eight pulses of the read clock b, and the output is input to a half-clock delay circuit 6, which is configured as a parity counter as shown in FIG. 5(d). Outputs pulse d for numerical memory. Further, the 18 frequency divider circuit 5 outputs one pulse for every 18 pulses of the read clock b,
The output is input to the half clock delay circuit 7, and the circuit is fj
A pulse e for comparison between the parity count value and the parity bit value as shown in Ss diagram (e) is output.

On the other hand, the input data a and read clock b are input to an 8-bit shift register 8. The shift register outputs input serial data as 8-bit parallel data. QA is the least significant bit and QH is the next most significant bit.

The output parallel data is input to the parity counting circuit 9. In the counting circuit, rl(2) among the inputs A-H.
If the number is odd, it outputs ro (2) J to EVEN, and if the number of inputs A-H is even, 1 (2) J (7) outputs 1 (2) to EVEN. In the case of input data a, the hexadecimal number rlA (h)J is rl(
Since the number of "2)" is three, ro (2) J is output to EVEN of the counting circuit 9, and r2B in hexadecimal
Since the number of rl(2)J in (h)J is four, rl(2)J is output to EVEN of the counting circuit 9.

The output from EVEN of the counting circuit 9 is input to a 2-bit shift register 10. The parity count memory pulse d from the half-clock delay circuit 6 is input to the shift register, and the first pulse d changes the parity count value of the hexadecimal data rlA (h)J. 0(2)" is stored in the lower bit QA of the shift register 10, and then the hexadecimal data "2B (h
) J's parity count rl(2)" is the shift register 1.
The parity count value ro of rlA(h)J, which was stored in QA so far,
2) J is shifted up to QB.

The memory values of the shift register 10 are each input to one input terminal of an XOR gate 11.12. These X
The outputs QB and QA of the shift register 8 are input to the other input terminal of the OR gate, respectively. The X
The OR gate has rO(2)J when the two inputs are the same.
and if the two inputs are different, it outputs "rl(2)".

The outputs of the XOR gates ll and 12 are respectively D
-7 is input to lip-flops 13 and 14.

As shown in FIG. 5(8), the comparison pulse e is outputted from the half-clock delay circuit 7 after the 18th pulse of the read clock b, and is outputted from the seven lip-flops 13.1.
At this point, the outputs QB and QA of the shift register 8 are the parity bit values rO(2)J and "1(2)" of the input data a, respectively.

Therefore, the output Q of the flip-flop 13 stores and outputs the comparison result between the parity value counted from the hexadecimal data rlA (h)J and the parity bit value of the data. If the comparison result output p1 is ro (2) J, it is determined that there is no error in the input data, and if the comparison result output pi is "1 (2)", it is determined that the input data has an error. be done. Similarly, the output Q of the flip-flop 14 has hexadecimal data r2B (h)J
The comparison result between the parity value counted from and the parity bit value of the data is stored and output.

If this comparison result output p2 is ro (2) J, it is determined that there is no error in the input data, and the comparison result output p2
rl(2)'', it is determined that there is an error in the input data.

Incidentally, at the time when the clearing pulse C is output, the pulse passes through the NOT gate 23 and is input to the flip-flop 13.1.
4 and these flip-flops are cleared.

The 8-bit shift register 8 is configured, for example, by the circuit shown in FIG. 6, where CLEAR is rl(2).
'', and the parity counting circuit 9 is constituted by, for example, the circuit shown in FIG.
) J.

The case where parity bits are assigned in units of 8 bits has been described above, but if parity bits are assigned in units of 16 bits in the conventional parity counting circuit as described above, the shift register 8 and the parity counting circuit 9 The problem was that the scale was doubled and the circuit became considerably larger at the gate level.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a parity counting method in which the circuit configuration does not become complicated even when the unit of adding parity bits is increased.

[Means for Solving the Problems] According to the present invention, the above objects are achieved.

In the method of counting the parity of the digital signal from a serial digital signal and a read clock synchronized with the signal, a switching pulse that switches from the read clock at a cycle corresponding to the parity counting unit data length is created, and the read clock is converted into a digital signal. Controlled by a signal and using the switching pulse, the input is alternately input to the two flip-flops, and after obtaining a parity count value of substantially unit data as the output of each flip-flop, the flip-flop is cleared. A parity counting method is provided, characterized in that parity is counted for each unit data length alternately and sequentially using two flip-flops.

[Example] Hereinafter, specific examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main part of the configuration of a parity determining circuit used to implement the parity counting method according to the present invention.

FIG. 2 is a pulse diagram for explaining the operation of the circuit, and the operation will be explained below with reference to this figure and FIG. 1.

FIG. 2(a) shows an example of input data a.

The data is rlA (h)J r2B(h
)", which is the same as that shown in FIG. 5(L) above.

FIG. 2(b) is an example of the read clock b that is input in synchronization with the above input data, and this is similar to that shown in FIG. 5(b) above.
It is similar to that of .

As shown in FIG. 1, the input data a and read clock b are input to a start bit detection circuit 3. When the detection circuit detects the start bit of input data a, it outputs a first clearing pulse C as shown in FIG. 2(e).

As shown in FIG. 1, the first clearing pulse C is input to a divide-by-8 circuit 4 and a divide-by-18 circuit 5. The above-mentioned read clock b is input to these circuits, and the above-mentioned first
When the clearing pulse C is input, the pulses of the read clock b are counted.

The divide-by-8 circuit 4 divides the frequency by 1 for every 8 pulses of the read clock b.
The second pulse shown in FIG. 2 (C') is output.
This is a clearing pulse. The output is input to a half clock delay circuit 6, which outputs a pulse d' for parity count memory as shown in FIG. 2(d'). Further, the 18 frequency divider circuit 5 outputs one pulse for every 18 pulses of the read clock b, and the output is outputted by the half clock delay circuit 7.
The circuit outputs a pulse e for comparison between the parity count value and the parity bit value as shown in FIG. 2(e).

The output d of the half clock delay circuit 6 is input to a T-flip-flop 17. The flip-flop is first cleared by the first clearing pulse C from the start bit detection circuit 3, and the state of Q is set to ro(2)J, and the state of Q is set to rl(2). The state of the output changes from "rl(2)" to "rl(2)" at the rising edge of the pulse.
0(2)'' or from ro(2)J to rl(2)J. Therefore, the output Q of the flip-flop is ro at the rising edge of the first pulse of the memory pulse d.
(2) From J to rl(2)'', and at the second pulse of memory pulse d, from rl(2)'' to ro(2
) changes to J. This is the switching pulse f shown in tj42 (f). Similarly, the output Q of the flip-flop changes from rl(2)'' to ro(2)J at the rising edge of the first H pulse of the memory pulse d, and changes from rl(2)'' to ro(2)J at the rising edge of the first H pulse of the memory pulse d. Pulse “0 (2
)" to "rl(2)". This is shown in Figure 2 (f
′) is the switching pulse f′ shown in FIG.

The input data a, the read clock b, and the switching pulse f' are input to the three-man power AND gate 18, and therefore, when the input data rlA(h)'' is input from the gate, the input is rl (2) J. A clock pulse is output only when In the case of the above data rlA (h)J, three pulses are output.

The output of the AND gate 18 is input to a first T-flip-flop 20. The flip-flop is first cleared by the first clearing pulse C from the start bit detection circuit 3, and the state of Q is set to ro (2) J. The initial state is ro (2) J, and the hexadecimal number rlA (h) J
In this case, three pulses are input, so the subsequent output Q of the flip-flop 20 is rl(2).

As described above, the parity of the hexadecimal data rlA(h) is substantially counted, and the value rl(2) is inverted by the NOT gate 28 to become ro(2)J, and then 2 bits The signal is input to the shift register 10. The above-mentioned memory pulse d output from the half-clock delay circuit 6 is input to the shift register, and the parity count value ro(2) of the data rlA (h)J is input at the first pulse d of the memory pulse. ” is stored in the output QA.

Next, the first flip-flop 20 is cleared by the second pulse of the second clearing pulse C'.

As shown above, the input data a, the read clock b, and the switching pulse f are input to the three-man power AND gate 19, and therefore, the upper two data r2B (h) are input from the gate.
When J is input, a clock pulse is output only when the input is "1 (2)". In the case of the above data r2B (h)J, four pulses are output.

The output of the AND gate 19 is input to the second T-flip-flop 21. The flip-flop is first cleared by the first clearing pulse C from the start bit detection circuit 3, and the state of Q is set to ro (2) J. If the initial state is ro(2)'' and the hexadecimal number r2B(h)J, four pulses are input, so the output Q of the flip-flop 21 thereafter becomes ro(2)J.

As described above, the parity of the hexadecimal data r2B(h) is counted, and the value "0(2)" is the value of the NOT gate 2.
8 and input into the 2-bit shift register 10. At this point, the second pulse of the memory pulse d output from the half-clock delay circuit 6 causes the data to be "2B".
(h) Parity count value rl of J (2) J is stored in the output QA. At this time, the value previously stored in QA is shifted up and stored in QB.

The parity count values counted in the above manner and stored in QB and QA are respectively input to one input terminal of the XOR gates 11 and 12.

The input data a and read clock b are also input to the 2-bit shift register 22. The shift register converts serial data into 2-bit parallel data, where QA is the lower bit and QB is the upper bit.

The outputs QB and QA of the shift register 22 are respectively input to the other input terminals of the XOR game (11 and 12).

The outputs of the XOR game) 11 and 12 are respectively D
- input to flip-flops 13.14;

As shown in FIG. 2(e), the comparison pulse e is output from the half clock delay circuit 7 after the 18th offset pulse of the read clock b, and is outputted from the flip-flop 13.1.
4, so at this point it is the output QB of the shift register 22.

QA is the A integrity bit value r of the above input data a, respectively.
o (2) J and rl (2) 1. Therefore, by the above comparison pulse e, hexadecimal data rlA (h)
The result of comparing the parity value counted from J and the parity bit value of the data is stored in the output Q of the 7-lip-flop 13. The output pt of this comparison result is ro (2) J
In the case of , it is determined that there is no error in the input data, and in the case where the comparison result output Pi is rl (2) J, it is determined that the input data has an error. Similarly, by the comparison pulse e, the comparison result between the parity value counted from the hexadecimal data r2B(h) and the parity bit value of the data is stored in the output Q of the 7-lip-flop 14. If the comparison result output p2 is ``ro(2)'', it is determined that there is no error in the input data, and if the comparison result output p2 is ``rl(2)'', it is determined that the input data has an error. be done.

In addition, in Fig. 1, 23.24 is a two-man powered AND gate, 25.28 is a two-man powered NOR gate,
27 is an OR gate operated by two people, and 29 is a NOT gate.

In the above embodiment, parity bits (y) are added in units of 8 bits, but parity bits can also be added in units of 16 bits or any other suitable number of bits. Furthermore, although the above embodiment has been described with respect to a 2-byte information signal, parity counting and determination can be performed in the same manner for information signals of other amounts.

In this embodiment, the data parity counting circuit has two sets of one three-man-powered AND gate 18 and one flip-flop 20 as shown in FIG. Therefore, even if the unit of parity bit addition is increased, the circuit configuration will not become complicated.

FIGS. 3(b) to 3(e) are diagrams showing examples of parity counting circuits that operate in the same manner as in FIG. 3(a).

In FIG. 3(b), 32 is a two-man AND gate, 30 is an XOR gate, and 31 is a D-flip-flop.

In FIG. 3C, 33 is a three-man power AND gate, and 34 is a D-flip-flop.

In FIG. 3(d), 35 is a three-man powered NAND gate, and 36 is a JK-7 lip-flop.

In FIG. 3(e), 37 is a three-man NAND gate, and 38 is an R3 flip-flop.

In FIG. 3, ``■'' to ``■'' respectively indicate the same input or output, ``■'' indicates input data, ``■'' indicates a read clock, ``■'' indicates a switching pulse, ``■'' indicates a clear input, and ``■'' indicates an output.

[Effects of the Invention] According to the present invention as described above, the clock input of the flip-flop is controlled using the data input, and the parity regarding unit data is sequentially counted by alternately performing switching between two processing destination systems. Therefore, even if the unit of adding parity bits increases, the circuit configuration does not become complicated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part of the structure of a parity determining circuit used to implement the parity counting method according to the present invention, and FIG. 2 is a pulse diagram for explaining the operation of the circuit. FIG. 3 is a diagram of the parity counting circuit. FIG. 4 is a block diagram showing the main part of the configuration of a conventional parity judgment circuit, FIG. 5 is a pulse diagram for explaining the operation of the circuit, and FIGS. 6 and 7 are respective diagrams of the circuit. FIG. 2 is a diagram showing a shift register and a parity counting circuit that constitute the circuit. Agent Patent Attorney Seki Yamashita Children 2 Figure 3 Figure 3 Procedure Amendment Belt January 28, 1988 Commissioner of the Patent Office Kunio Ogawa Indication of Case Patent Application No. 1983-33454 2 Name of Invention Parity Counting method 3 Relationship with the person making the amendment Patent applicant name (+00) Canon Co., Ltd. 4 Agent address 40 Toranomon, 5-13-1 Toranomon, Minato-ku, Tokyo
Mori Building drawing Figure 3

Claims (1)

[Claims] (1) In the method of counting the parity of the digital signal from a serial digital signal and a read clock synchronized with the signal, a switching pulse that switches from the read clock at a cycle corresponding to the parity counting unit data length is created, and the parity of the digital signal is The clock is controlled by a digital signal, and the switching pulse is used to alternately input the clock to the two flip-flops, and after obtaining a parity count value of substantially unit data as the output of each flip-flop, the flip-flop is cleared. A parity counting method characterized in that two flip-flops alternately and sequentially count parity for each unit data length.