JP2870052B2 - Silence state detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silent state detecting circuit, and more particularly to a silent state detecting circuit suitable for a digital audio device.

2. Description of the Related Art In a digital audio device, a silent state such as between music pieces is performed by detecting digital data having an analog value of 0 volt or a value close thereto.

[Problems to be solved by the invention]

As described above, the silent state has been detected from the digital data. However, if there is a DC offset in the input digital data, the silent state cannot be detected, and therefore muting must be performed. Therefore, there is a problem that noise cannot be removed in a silent state.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a silent state detecting circuit capable of reliably detecting a silent state regardless of the presence or absence of a DC offset.

[Means for solving the problem]

A silent state detection circuit according to the present invention, DC detection means for detecting whether the input digital data is DC,
Low-level detection means for detecting whether or not the input data is a minute level close to substantially zero level; and, as a result of the detection by the DC detection means and the detection by the low-level detection means, the input digital data is DC, and the input data is A silent determining means for determining a silent state when it is simultaneously determined that the level is a minute level is provided.

[Action]

According to the present invention, in the DC detection means, continuous data values are constant, that is, input digital data
The presence of any level of direct current is detected.

In addition, the low-level detection means sets
It is detected that the digital data input from the middle-order bit is a minute level.

When it is detected that the input digital data is direct current and that the input data is at a very low level, it is determined that there is no sound.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

In the configuration of FIG. 1, serial digital audio data (hereinafter referred to as input data) DA supplied to a terminal 1 is composed of an L channel silence detection circuit 2, an R channel silence detection circuit 3, and a timing controller. 4
Are supplied respectively.

The timing controller 4 includes the input data DA described above.
In addition, a clock signal CLK is supplied via a terminal 5, a mode select signal MO via a terminal 6, and the like.

The mode select signal MO includes the number of bits per word and the data arrangement, for example, LS within a word.
This is for specifying the arrangement of B and MSB, the width of the load window pulse WL, and the measurement time of the timer.

In the timing controller 4, the clock signal CLK,
Mode select signal MO, input data shown in FIG. 3A
Based on DA, the LR clock LR CLK shown in FIG.
The bit clock BCK shown in FIG. 3C, the load window pulse WL shown in FIG. 3D, the window pulse W2 for DC detection shown in FIG. 3E, and the silence data detection shown in FIG. Window pulses W3 are respectively formed.

In addition to the above-described input data DA, the timing controller 4 supplies load noise pulses WL, window pulses W2 for direct current detection, and window pulses for noiseless data detection to the silence detection circuits 2 and 3 for the L and R channels.
W3 and bit clock BCK are supplied, respectively. When a silence state is detected by the silence detection circuits 2 and 3, a timer reset signal RS is generated. The timer reset signal RS is output from the silence detection circuit 2 to the timer circuit 7.
The silence detecting circuit 3 supplies the timer circuit 8 with each other.

The timer circuits 7 and 8 are supplied with a timer reset signal RS supplied from the silence detection circuits 2 and 3 and a bit clock BCK supplied from the timing controller 4, respectively. The timer circuits 7 and 8 perform a time counting operation for counting the bit clock BCK. When the timing operation is continued for a predetermined time, a mute signal MUT for the L channel or the R channel is formed and is taken out from the terminals 9 and 10.

FIG. 2 shows details of the silence detection circuit 2 for the L channel. Since the structure of the silence detection circuit 3 for the R channel is the same, the description of the silence detection circuit 3 is omitted. In the following description, it is assumed that all the input data DA represent words on the L channel side.
The clear pulse CL supplied to the terminal 21 is supplied for initialization when the system is started.

The silence detection circuit 2 includes a DC detection circuit 22 for detecting whether the input data DA is DC, and a low level detection circuit 23 for detecting whether the input data DA is at a minute level. ing. And input data DA
Is detected as a silent state when the input data DA is detected to be a minute level, and a high-level timer reset signal RS is formed and supplied to the timer circuit 7.

The serial input data DA supplied to the terminal 24 is L,
The data of each channel of R is alternately arranged in units of one word, and the input data DA of one word is composed of, for example, 16 bits. The input data DA is supplied to the serial-to-parallel conversion circuit 25 sequentially from the MSB side as shown in FIG. 3A.

The serial-to-parallel conversion circuit 25 is constituted by, for example, a shift register, and the input data DA is taken into the serial-to-parallel conversion circuit 25 in synchronization with the bit clock BCK supplied via the terminal 26. It is converted to parallel data. The lower 5 bits of the input data DA of one word are supplied in parallel to the selector 27 from the output terminals Q1 to Q5. Also, the input data DA generated at the output terminal Q1 is
The signal is supplied to an OR gate 28 and further supplied to an OR gate 30 via an inverter 29.

In the selector 27, the window pulse W2 for DC detection, which is supplied to the select terminal via the terminal 31, is supplied to the selector 27 in FIG.
As shown in (1), when the level becomes low, the selection of the terminal on the input side is switched from terminals B1 to B5 to terminals A1 to A5. As a result, the terminals Q1 to Q5 of the serial-to-parallel conversion circuit 25
Thus, the lower 5 bits of the input data DA in the n-th word are selected by the selector 27. These 5 bits are supplied to the D flip-flop 32 from the output terminals Y1 to Y5 of the selector 27. The selection of the terminal on the input side of the selector 27 is performed by the above-described window pulse W2 rising,
When the level becomes high, the terminals A1 to A5 are switched again to the terminals B1 to B5.

Before the input data DA of the n-th word is supplied to the D flip-flop 32, the input data DA of the (n-1) -th word is supplied to the D flip-flop 32.
Are stored, but when the input data DA of the n-th word is supplied, the lower 5 bits of the input data DA of the n-th word are supplied at the timing of the bit clock BCK.
Bits are taken from terminals D1-D5, respectively. afterwards,
The lower 5 bits of the input data DA of the n-th word are output from the terminals Q1 to Q5 on the output side to the terminals B1 to B5 of the selector 27, the terminals A1 to A5 of the selector 33, and the exclusive OR gates 34 to
At one end of 38, each is supplied.

The lower 5 bits of the input data DA of the n-th word held in the D flip-flop 32 are fed back to the terminals B1 to B5 of the selector 27, and this input data DA is
In synchronization with the bit clock BCK, the terminals B1 to B5 and the terminals Y1 to Y
After 5, it is supplied to the D flip-flop 32 again.
During the period when the window pulse W2 is at the high level, the lower 5 bits of the input data DA of the n-th word correspond to the selector 2
7. The process of circulating through the D flip-flop 32 is repeated.

In the selector 33, a window pulse W2 for DC detection, which is supplied to the select terminal via the terminal 31, is supplied to the selector 33 in FIG.
As shown in (5), when the level becomes low, the selection of the input side terminal is switched from the terminals B1 to B5 to the terminals A1 to A5. As a result, the input data in the (n-1) th word supplied from the terminals Q1 to Q5 of the D flip-flop 32
The lower 5 bits of DA are selected by the selector 33.
These 5 bits are output from the terminals Y1 to Y5 on the output side of the selector 33.
It is supplied to a D flip-flop 39.

The terminal on the input side of the selector 33 is switched from the terminals A1 to A5 to the terminals B1 to B5 again when the above-mentioned window pulse W2 rises and goes to a high level.

The input data DA of the (n-1) th word is D
Before being supplied to the flip-flop 39, the D flip-flop 39 holds the lower 5 bits of the input data DA of the (n−2) th word. When the input data DA of the (n-1) -th word is supplied, the lower 5 bits of the input data DA of the (n-1) -th word at the timing of the bit clock BCK.
Bits are taken from terminals D1-D5. Then, the (n
-1) The lower 5 bits of the input data DA of the word are
The output terminals Q1 to Q5 supply the signals to the terminals B1 to B5 of the selector 33 and the other ends of the exclusive OR gates 34 to 38, respectively.

The (n-1) th data stored in the D flip-flop 39
The lower 5 bits of the input data DA of the second word are fed back to the terminals B1 to B5 of the selector 33, and the input data DA passes through the terminals B1 to B5 and the terminals Y1 to Y5 in synchronization with the bit clock BCK, and again. , D flip-flop 39. While the window pulse W2 is at the high level, the process of circulating the lower 5 bits of the input data DA of the (n-1) th word through the selector 33 and the D flip-flop 39 is repeated.

In the exclusive OR gates 34 to 38, the lower 5 bits of data of the n-th word supplied from the D flip-flop 32 and the lower 5 bits of the (n-1) th word supplied from the D flip-flop 39 Match detection with 5-bit data is performed. When the input data DA is direct current, since the lower 5 bits of the n-th data and the lower 5 bits of the (n-1) -th data coincide with each other, the low-order bits from the exclusive OR gates 34 to 38 are used. Level signals are respectively output, and the signals are supplied to one end of a NOR (NOR) gate 41 via an OR gate 40.

As described above, the terminal of the serial-to-parallel conversion circuit 25
From Q1, 16-bit input data DA that constitutes one word
Among them, upper and middle (MSB side) 12-bit data are serially supplied to one end of an OR gate 28 and one end of an OR gate 30 via an inverter 29, respectively.

Since the input data DA is a 2'S complement code, if its analog value is very small, the middle 12 bits of the input data DA are all low level ("0") or all high level ("0"). “1”). Therefore, if the analog value is low, low level ("0") data is supplied to one of the OR gates 28 and 30, and high level ("1") is supplied to the other. By changing the mode select signal MO, the bit to be detected can be the upper and middle 14 bits.

By the way, of the input data DA of one word, upper and middle 12
The bits are level detected by the low level detection circuit 23, and the lower 5 bits are DC detected by the DC detection circuit 22 as described above. Therefore, the least significant bit of the upper and middle 12 bits is duplicated and used in the low level detection circuit 23 and the DC detection circuit 22, but this prevents erroneous detection of a silent state. That's why.

If the 1-bit value is not used repeatedly, for example, the D flip-flop 42,
Even when the output of 43, that is, the high level (“1”) or the low level (“0”) is inverted for each word, the low level detection circuit 23 determines that the output is a minute level. If the direct current detection circuit 22 detects that the current is direct current, there is a possibility that a silence state may occur even if the state is not a silence state. Therefore, the DC detection circuit 22, the low level detection circuit 23
In both cases, one of the middle 12 bits is redundantly used for detection, so that only when the output polarity is not inverted and a minute DC is present in the input data DA, the silent state is obtained. Detection is performed correctly.
Incidentally, the bits used for preventing the erroneous detection are not limited to the above-described example, and bits at arbitrary positions in the upper and middle bits can be used. Of these, a plurality of bits can be used.

The outputs from the terminals Q of the D flip-flops 42 and 43 are fed back to the other ends of the OR gates 28 and 30, respectively. The output of OR gate 28 is AND gate 4
4, 45, and the output of OR gate 30 is AND gate 4.
It is supplied to one end of each of 6, 45. Also, And Gate 4
The other end of each of 4 and 46 is supplied with a load window pulse WL for low level detection shown in FIG.

In the load window pulse WL, the period of T1F is, for example, 8.5 bit clock BCK, and the period of T1R is, for example, 12 or 14 bit clock BCK. When the load window pulse WL is at a low level, the outputs of the AND gates 44 and 46 are connected to the terminals D of the D flip-flops 42 and 43.
, Respectively. As shown in FIG. 3D, at the beginning of each word, the load window pulse WL is at a high level, and the outputs of the AND gates 44 and 46 are at a low level. From the output terminal Q of the flip-flops 42 and 43, a low-level (“0”) signal is fed back to the other ends of the OR gates 28 and 30, respectively.

Accordingly, the output of the OR gate 28 becomes low level ("0") only when all the middle 12 bits of the input data DA are low level ("0"), and even one bit of the 12 bits becomes high level ("0"). At the time of "1"), the output of the OR gate 28 becomes high level ("1"). Since the middle 12 bits of the input data DA are supplied to the OR gate 30 via the inverter 29, the output of the OR gate 30 is output only when all the above 12 bits are at the high level ("1"). It becomes low level (“0”). Therefore, when the upper 12 bits of the input data DA are all at low level (“0”), all of them are at low level (“0”).
4. Detected by the D flip-flop circuit. Also,
When all the upper 12 bits of the input data DA are at the high level ("1"), it is detected by the OR gate 30, the sink gate 46, and the D flip-flop 43 that they are all at the high level ("1"). You.

The outputs of the OR gates 28 and 30 are supplied to the AND gate 45. The output of the AND gate 45 is supplied to the terminal A on one input side of the selector 49 and the NOR gate 41. Selector 49
Is supplied to the D flip-flop 50, and the signal output from the D flip-flop 50 is fed back to the other input terminal B of the selector 49. The selector 49 and the D flip-flop 50
A signal output from the AND gate 45 only during a period in which the load window pulse WL is at a low level is taken in via a selector 49. During the period when the load window pulse WL is at the high level, the selector 27 and the D flip-flop 32
As in the case of, the signal output from the AND gate 45 is
The process of circulating through the selector 49 and the D flip-flop 50 is repeated.

The output of AND gate 45 is
It becomes low level only when all 12 bits are low level (“0”) or high level (“1”). The signal output from the AND gate 45 and the signal output from the OR gate 40 of the DC detection circuit 22 are supplied to the NOR gate 41. When the output of the NOR gate 41 is at a high level, that is, when the outputs of the OR gate 40 and the AND gate 45 are both at a low level, it is detected that the input data DA is a DC and minute level, that is, a silent state.

A selector 51 and a D flip-flop 53 are provided on the output side of the NOR gate 41, and a signal output from the D flip-flop 53 is taken out from a terminal 54 as a timer reset signal RS. As a control signal of the selector 51, a terminal 52
Supplies a window pulse W3 shown in FIG. 3F.
Only when the window pulse W3 is at the low level, the output of the NOR gate 41 is taken into the D flip-flop 53.
When the window pulse W3 is at the high level, the process of circulating the signal output from the D flip-flop 53 through the selector 51 and the D flip-flop 53 is repeated as in the case of the selector 27 and the D flip-flop 32 described above.

This timer reset signal RS is supplied to the timer circuit 7. In the timer circuits 7 and 8, after a counter (not shown) is reset by the above-described high-level timer reset signal RS, the timer circuit starts counting time by counting the bit clock BCK supplied from the timing controller 4. . While the timer reset signal RS maintains the high level, the timekeeping operation is continued. If this timekeeping operation is continued for a predetermined time, for example, 0.1 or 0.3 seconds, it is determined that there is no sound, and a mute signal MUT is output to perform muting.

If the timer reset signal RS goes low during the time counting operation of the timer circuits 7 and 8, it means that the analog value of the input data DA is not DC and is not at a minute level. The timing operations of the circuits 7 and 8 are stopped, and the mute signal MUT is not output.

Accordingly, even if the input data DA has an arbitrary level of DC offset, a silent state can be detected and muting can be reliably performed, so that the noise level in a silent state can be greatly improved.

Also, the least significant bit of the upper and middle 12 bits of the data of one word is determined by the low level detection circuit 23 and the DC detection circuit.
By using both of them for detection, the silent state can be correctly detected, and erroneous detection can be prevented.

〔The invention's effect〕

According to the silence state detection circuit according to the present invention, when the two conditions that the analog value of the input digital data is DC and the level of the digital data are minute are satisfied, the silence state is determined. Therefore, even if there is a DC offset in the input digital data, a silent state can be reliably detected, and muting can be performed when there is no sound, so that the noise level in the silent state can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a silence detecting circuit, and FIG. 3 is a timing chart showing circuit operation. Explanation of main symbols in the drawings 2, 3: Silence detection circuit, 7, 8: Timer circuit, 22: DC detection circuit, 23: Low level detection circuit, 41: NOR gate, 45: AND gate, DA: Digital audio data.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11B 15/087 G11B 20/10 G11B 27/22

Claims (1)

(57) [Claims] 1. DC detection means for detecting whether or not input digital data is DC, low level detection means for detecting whether or not the input data is a minute level close to substantially zero level, and said DC detection means And the detection by the low-level detection means, the input digital data is direct current, and, when it is simultaneously determined that the input data is at a very low level, silence determination means for determining a silent state. A silent state detection circuit provided.