JP3225821B2 - Pulse width selection signal output device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pulse width selection signal output device capable of selecting a pulse width.

[0002]

2. Description of the Related Art An example of a conventional pulse width selection signal output device will be described below with reference to FIGS. FIG. 3 is a circuit diagram showing the configuration of this device, and FIG. 4 is an operation waveform diagram thereof.

As shown in FIG. 3, this device comprises a binary counter 1, decoders 2 to 4, a selector circuit 9 comprising NAND gate circuits 5 to 8, a D-flip-flop circuit 10, and an R-flip-flop. And a waveform shaping circuit 12 composed of an S latch circuit 11.

[0004] The binary counter 1 counts a clock signal a applied from a clock signal input terminal 13, and its count value is reset by a reset signal b from a reset signal input terminal 14.

[0005] The decoders 2 to 4 include a binary counter 1
Of the corresponding selector circuit 9
The respective output signals c to e are supplied to one input terminal of the NAND gate circuits 5 to 7 of FIG.

The selector circuit 9 responds to selection signals f to h supplied from the selection terminals 15 to 17 to the other input terminals of the NAND gate circuits 5 to 7, respectively.
One of the decoded output signals c to e by
The D-flip-flop circuit 1 of the waveform shaping circuit 12
0 is supplied to one input terminal.

In the waveform shaping circuit 12, the D-flip-flop circuit 10 outputs a signal i in accordance with the decoded output signal selected by the selector circuit 9 and the clock signal a applied to the other input terminal. -S It is supplied to one terminal of the latch circuit 11.

The RS latch circuit 11 generates an output signal j at an output terminal 18 according to the output signal i of the D flip-flop circuit 10 and the reset signal b supplied to the other input terminal. This output signal j is a signal having a width equal to the range from the reset signal b to the output signal i of the D-flip-flop circuit 10.

The above operation will be described in more detail with reference to FIG. The binary counter 1 is reset by the first reset signal b, and counts the clock signal a until the next reset signal is applied. The decoders 2 to 4 respectively decode the count values A, B, and C of the binary counter 1 and generate output signals c, d, and e. Here, the waveforms of the decode output signals c, d, and e are not necessarily limited to the pulse waveforms shown in the figure, and the count values A, d after the arrival of the reset signal b.
It suffices if the first output is obtained for each of B and C.

One of these decode output signals c to e is supplied from select terminals 15 to 17 to NAND gate circuits 5 to 17.
7 is set to “Hi” or “L”.
o ". As an example, the output signal c
When selecting the signal d among the signals e through e, for example, the selection signal g applied to the selection terminal 16 is set to “Hi” level, and the selection signals f and h applied to the other selection terminals 15 and 17 are set to “L”.
o "level. The selected decode output signal d is applied to the input terminal D of the D-flip-flop circuit 10 of the waveform shaping circuit 12, and the clock signal a is supplied to the input terminal CK of the waveform shaping circuit 12. The flip-flop circuit 10 generates, at the inverted output terminal, an output signal i having a trailing edge synchronized with the count value of the binary counter 1 when the count value becomes B. The output signal i is RS latched By setting the reset signal b as the reset signal for the circuit 11 as a set signal,
The RS latch circuit 11 generates an output signal j from its inverted output terminal. The output signal j is a pulse signal of “Hi” level during a period from the reset signal “b” immediately before the start of counting to the count value “B”. Here, by setting the level of the selection signal f or h applied to the selection terminals 15 to 17 to “Hi”, the trailing edge is set to the count value A or C.
Can be synchronized. Therefore, the output terminal 18
The output signal j obtained as described above can have three types of pulse widths depending on the signal levels of the selection signals f to h to the selection terminals 15 to 17.

[0011]

In such a pulse width selection signal output device, if the pulse width of the output signal j obtained at the output terminal 18 is to be made variable, the number of decoders corresponding to the type of the desired width is required. , And the desired number of selection terminals.

According to the present invention, it is possible to obtain a pulse width selection output signal having the number of selection terminals as an exponent of 2 with a simple circuit configuration. In particular, in the integration, the pulse width is variable with a small number of elements. It is an object to provide a pulse signal output device that can perform the above-described operations.

[0013]

In order to solve the above-mentioned problems, a pulse width selection signal output device according to the present invention has a reset signal input terminal and a clock signal input terminal, and a binary counter reset by the reset signal. A decoder for decoding the count value output of the binary counter, and a plurality of exclusive OR gates for supplying a bit output lower than the least significant bit of the bits supplied to the decoder from the binary counter to one input terminal A circuit, a plurality of selection input terminals for supplying a signal to the other input terminal of the plurality of exclusive OR gate circuits, and an AN for outputting a logical product output of an output of the exclusive OR gate circuit and an output of the decoder
A D-gate circuit, a D-flip-flop circuit in which a logical product output by an AND gate circuit is supplied to a D input terminal, and a clock signal is supplied to a clock signal input terminal, and an output of the D-flip-flop circuit is supplied to one input terminal Is supplied, and a reset signal is supplied to the other input terminal.
A latch circuit is provided, and an output terminal to which an output of the RS latch circuit is supplied.

Thus, the selection by one decoder can be performed.
If the number of selection terminals is 3, 8 (= 2 ^Three) Pulse width
Can be selected and output.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of this example, and FIG. 2 is an operation waveform diagram thereof. In FIG. 1, components corresponding to those of the device shown in FIG. 3 are denoted by the same reference numerals.

The binary counter 1 counts a clock signal a from a clock signal input terminal 13 and is reset by a reset signal b from a reset signal input terminal 14. The decoder 19 decodes the count value A of the binary counter 1 and generates a decoded output c. The timing selector 20 includes a plurality of exclusive OR gate circuits 21 to 23 and an AND gate circuit 24.
It is composed of Exclusive OR gate circuit 21
23 are supplied with bit outputs Ql, Qm, Qn lower than the least significant bit of the binary counter 1 being decoded by the decoder 19, respectively, and the other input terminals are selected. Input signals f, g, and h applied to terminals 15 to 17 are supplied, respectively. The AND gate circuit 24 is connected to these exclusive O
Outputs of R gate circuits 21 to 23 and output c of decoder 19
And the result is taken as the output of the timing selector 20. The waveform shaping circuit 12 is a D-flip-flop circuit 1
0 and an RS latch circuit 11. The clock signal a from the clock signal input terminal 13 is applied to the clock signal input terminal of the D-flip-flop circuit 10,
Output signals of the timing selector 20 are supplied to the input terminals. A reset signal from a reset signal input terminal 14 is supplied to one input terminal of the RS latch circuit 11, and an output signal i of the D-flip-flop circuit 10 is supplied to the other input terminal. The output terminal of the RS latch circuit 11 is connected to the output terminal 18 to extract the output signal j, and a pulse signal having a width between the output signal i of the D-flip-flop circuit 10 is obtained by the reset signal b.

The operation of the apparatus having the above configuration will be described below. In FIG. 2, a binary counter 1 counts a clock signal a and is reset by a reset signal b. The count value A is decoded by the decoder 19 to obtain a decode output c. The count value B is decoded by the Qm output of the binary counter 1 and the "Low" level input signal of the selection terminal 16, and the Ql output and Qn of the binary counter 1 are decoded. "Lo" of the output and selection terminals 15 and 17
The count value C is decoded by the w "level input signal. These decoded outputs are supplied to the input terminal of the D-flip-flop circuit 10 of the waveform shaping circuit 12 as the output of the timing selector 20, and the binary counter 1 Is used as the clock signal for the D-flip-flop circuit 10, an output signal i can be obtained at the output terminal of the D-flip-flop circuit 10 immediately after the output signal of the timing selector 20. By using the output signal i as the set signal of the RS latch circuit 11 and using the reset signal b as the reset signal, the output signal j can be obtained from the inverted output terminal of the RS latch circuit 11.

The output signal j is a pulse signal which goes to the "Hi" level during the period of the count value (A + α) from the reset signal b. You can choose. Therefore, by outputting the output signal j to the output terminal 18, it is possible to obtain an output signal whose pulse width can be varied by the input signals to the selection terminals 15 to 17.

[0019]

According to the present invention, it is possible to obtain a pulse width selection output signal having the number of selection terminals as an exponent of 2 with a configuration having one decoder, and particularly, a device having a small number of integrated circuits. The pulse width can be varied by the number
Very useful in practice.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a pulse width selection signal output device according to the present invention.

FIG. 2 is an operation waveform diagram of the embodiment of the present invention shown in FIG.

FIG. 3 is a circuit diagram of a conventional pulse width selection signal output device.

FIG. 4 is an operation waveform diagram of a conventional pulse width selection signal output device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Binary counter 10 D-flip-flop circuit 11 RS latch circuit 12 Waveform shaping circuit 13 Clock signal input terminal 14 Reset signal input terminal 15-17 Selection terminal 18 Output terminal 19 Decoder 20 Timing selector 21-23 Exclusive OR gate Circuit 24 AND gate circuit

Claims (1)

(57) [Claims] A binary counter having a reset signal input terminal and a clock signal input terminal, the binary counter being reset by the reset signal, a decoder for decoding a count value output of the binary counter, and a decoder supplied from the binary counter to the decoder. A plurality of exclusive OR gate circuits in which a bit output lower than the least significant bit of the bits is supplied to one input terminal, and to supply a signal to the other input terminal of the plurality of exclusive OR gate circuits. AND outputs an AND output of outputs of the plurality of exclusive OR gate circuits and the outputs of the decoders
The AND output is supplied to a gate circuit and a D input terminal,
A D-flip-flop circuit to which the clock signal is supplied to a clock signal input terminal;
An RS latch circuit to which an output of the flip-flop circuit is supplied and the reset signal is supplied to the other input terminal;
An output terminal to which an output of the RS latch circuit is supplied.