JP3353543B2 - Control signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel converter and a control signal generator used in a parallel / serial converter.

When converting an input signal into a parallel signal or a serial signal through a serial / parallel converter or a parallel / serial converter, a control signal generation circuit using a counter or a decoder generates a control signal when the timing cycle becomes large. Since the delay in performing the conversion increases, the operation speed of the entire conversion unit decreases.

Accordingly, it is an object of the present invention to suppress an increase in delay when generating a control signal.

[0004]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example. In the figure, the counter 31 starts a counting operation from an initial value (for example, “0000”), sends a carry when the count value reaches “1111”, and repeats the counting operation again from the initial value.

[0005] The decoder section 32 decodes a predetermined count value and sends out a decoded output as a control signal. However, when the period of the control signal is increased, the number of bits of the counter is increased, so that the configuration is complicated and the delay until a predetermined count value is increased.

[0006]

As described above, since the control signal generation circuit is composed of a counter and a decoder for decoding the output of the counter, if the period of the control signal becomes longer, the number of bits of the counter increases. , The delay amount increases.

Further, since the number of inputs to the decoder section increases, the configuration of the decode section becomes complicated, and the delay in this section also increases. That is, there is a problem that the delay of the control signal generation circuit increases and the operation speed of the entire circuit decreases.

An object of the present invention is to suppress an increase in control signal generation delay.

[0009]

According to a first aspect of the present invention, when a reset signal is applied, the first-stage bistable element outputs an "H" level, and the second to n-th bistable elements. Are turned off when a load pulse is applied between each stage of the n-stage shift register connected so as to simultaneously output the "L" level (n
-1) ORing the input control means between the first-stage bistable element and the n-th bistable element to obtain the logical sum of the load pulse and the output of the n-th bistable element Means are provided respectively.

Then, the control circuit generates a control signal by circulating only one pulse sent from the bistable element in the first stage, extracting the output of the bistable element specified in advance. Second
According to the present invention, in the above control signal generation circuit, when the reset signal is applied, the output is cleared when the load pulse is applied, the output number of the OR means is counted from an initial value, and a carry is sent when the count value reaches a predetermined count value. Counting means and path switching means are provided.

When the carry is not applied, the path switching means outputs the output of the n-th stage bistable element when the carry is not applied, and outputs the output of the m-th stage (n> m positive integer) when the carry is applied. An output is added to the logical sum means so that the period of the control signal to be generated can be switched.

According to a third aspect of the present invention, the path switching means includes a switch means for sending the output of the bistable element selected in accordance with the state of application of the carry to the logic means, and an off state when the carry is applied. Switching means for applying the output of the m-th stage bistable element to the selector in the state and turning off the input control means provided on the input side of the (m + 1) -th stage bistable element; And bypassed (m + 1)
The output of the bistable element from the stage to the n-th stage is set to “0”.

[0013]

According to the first aspect of the present invention, when a reset (XRST) signal is input, the first-stage bistable element outputs "1", and
The n-th stage bistable elements are simultaneously cleared and are turned off when a load pulse is inputted between the respective stages of the n-stage shift registers connected so as to output "0". Insert input control means.

[0014] In addition, between the first-stage bistable element and the n-th bistable element, there is provided a logical OR means for calculating the logical sum of the load pulse and the output of the n-th bistable element. Then, by the input of the reset signal or the output of the OR means,
By circulating only one pulse sent from the first-stage bistable element, the control signal is generated by extracting the output of the previously specified bistable element.

According to a second aspect of the present invention, the configuration of the first aspect of the present invention includes:
It is cleared when a reset signal is applied, and the output of the OR means is counted from the initial value when a load pulse is applied. When the count value becomes all "1", a carry is sent out and the count is repeated again from the initial value. Means and a path switching means for applying the output of the bistable element at the nth stage when no carrier is applied and the output of the bistable element at the mth stage when the carry is applied to the logical sum means.

The cycle of the control signal can be switched according to the output of the path switching means. According to a third aspect of the present invention, the path switching means includes a switching means and a switching means, and outputs the bypassed bistable elements from the (m + 1) th stage to the nth stage to "0".

That is, by using an n-stage cyclic shift register, the delay amount of the counter can be set to a constant low value irrespective of the size of the timing cycle, and the input control means and the logical sum means can be provided in the cyclic shift register. Is provided.

As a result, only one pulse of one clock width can be circulated in the n-stage cyclic shift register at all times. Then, the control signal is generated by taking the logical sum of the outputs of the plurality of bistable elements in the n-stage cyclic shift register. As a result, it is possible to suppress an increase in delay when generating the control signal.

[0019]

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG.
FIG. 3 is a diagram for explaining the operation of FIG. 1, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG.

Here, the reference numerals on the left side in FIGS. 2 and 4 show the waveforms of the same reference numerals in FIGS. 1 and 3. Hereinafter, FIG.
1 and 3 will be described with reference to FIG. 4. The flip-flop of the embodiment corresponds to a bistable element in the claims.

In FIGS. 1 and 3, FF ₁ to FF in FIG.
FF ₁₀ is a flip-flop, 11 to 19 and 21 to 24 are AND gates, and 25 is a quaternary counter. Also the clock
When the number assigned to CK is ₁ , the first clock is CK1, but the CK supplied to each element is omitted in FIGS.

First, in FIG. 1, the output of FF ₁ is
While the reset signal (hereinafter abbreviated as XRST signal) input to the pin is fixed to "1" while "0", the output corresponding to the state of the input signal is transmitted when it becomes "1". Also, FF ₂ ~
The output of the FF ₁₀ is cleared (CL) to the terminal "0" is cleared when XRST signal is inputted becomes "0".

The AND gates 11 and 12 load "0" (L
OAD) While the pulse is applied, it is in the ON state, so FF
₂ is CK ₂ which takes in the output "1" of FF ₁ and outputs "1",
FF ₃ takes in the output "1" of FF ₂ at CK ₃ and outputs "1".

[0024] It should be noted that, between XRST signal of CK ₁ and CK ₂ "0"
→ "1", so FF ₁ outputs the output "0" of OR gate 23 to CK ₂
And output "0". Where CK ₃ and CK ₄
The load pulse of "1" of 1 clock width between OR gate 23
Input to FF ₁ and AND gates 11 to 19 through FF ₁
Captures at CK ₄ and outputs "1". However, FF _{2 to} FF
₁₀ outputs takes in "0" to AND gates 11 to 19 outputs "0" in CK ₄ (see left part of b in FIG. 2-CK).

[0025] Thus, in the shift register composed of FF ₁ to ff ₁₀ will be present only one pulse of one clock width only. After this, since LOAD pulse is "0", all the AND gates 11 to 19 are turned on, in accordance with CK to be input in the region of CK ₄ ~CK ₁₃ of FIG. 2 "
1 "shifts sequentially, and the output of FF ₁₀ is OR gate 23
FF ₁ again, and only one pulse of 1 clock width taken in at CK ₁₄ circulates again (hereinafter FF _1).
~ FF ₁₀ , called a cyclic shift register including OR gate)
(Refer to the portion of the right side to -1 in FIG. 2B).

Then, for example, the OR gate 21 outputs FF ₁ , FF ₉ ,
ORed output of FF ₇ , OR gate 22 is FF _4, FF
₅ and FF ₆ are ORed and sent as control signals (see OUT-1 and OUT-2 in FIG. 2).

Next, FIG. 3 differs from FIG. 1 in that the quaternary counter 25, the path switching switch SW, and the AND gate 24
The provided cyclic path is to be switched to FF ₁ to ff ₁₀ and FF ₁ ~FF _8.

That is, the quaternary counter 25 is enabled every time the output of the OR gate 23 is applied to the EN terminal.
The clock CK input at this time is counted, and the count value is incremented from 0. And when the count value becomes 3,
Carry "1" from the CO terminal to the path switch SW and AN
D is sent to the gate 24, and the counting operation is repeated from 0 again.

Here, when the carry is "1", the path switching switch SW selects the B side, and outputs the output of the FF ₈ to the OR gate 23.
To FF ₁ and the quaternary counter 25. Since "0" is input to the AND gate 24, the output "0" is input to the AND gate 18
And the AND gate 18 also sends the output "0" to the FF ₉ .

Then, the FF ₉ adds the output "0" to the FF ₁₀ via the AND gate 19, and the FF ₁₀ also sends the output "0", so that the outputs of the bypassed FF ₉ and FF ₁₀ are both "0". " on the other hand,
In the same manner as described above, only one pulse of one clock width circulates on the path of the cyclic shift register composed of FF _{1 to} FF ₈ (see the right side of CK _{25 in} FIG. 4).

However, when the carry becomes "0", the path switching switch SW selects the A side, applies the output of the FF ₁₀ to the FF ₁ and the quaternary counter 25 through the OR gate 23, and outputs
The D gate 24 is turned on, and operates as in FIG.

It is to be noted that the circuit path is to make three rounds of the paths FF ₉ and FF ₁₀ and then one round of the paths FF _{1 to} FF ₈ . Furthermore, by decoding a count value, the decoded output by controlling the operation of the switch SW and the AND gate 24, FF ₁ ~
It can be set arbitrarily switching point FF ₁₀ and FF ₁ ~FF _8.

That is, as described above, the control signal can be generated with a high-speed constant delay irrespective of the count cycle, and further by combining with a configuration using a conventional counter,
Generation of a more complicated control signal can also be performed with a high-speed constant delay.

[0034]

According to the present invention as described in detail above, there is an effect that an increase in control signal generation delay can be suppressed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is a diagram illustrating the operation of FIG. 3;

FIG. 5 is a configuration diagram of a conventional example.

[Explanation of symbols]

11 to 19 AND gate 21 to 24 OR gate 25 Counter FF _{1 to} FF ₁₀ Flip-flop SW switch

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 27/00 H03K 23/00

Claims (3)

(57) [Claims] When a reset signal is applied, a first-stage bistable element outputs an “H” level, and a second to n-th stages (n ≧ n)
(Positive integer of 3) bistable elements are connected to output the "L" level at the same time. Between each stage of the n-stage shift register, the (n-1) number of which are turned off when a load pulse is applied. The input control means is provided between the first-stage bistable element and the n-th bistable element, and a logical sum means for taking a logical sum of the load pulse and the output of the n-th bistable element is provided, By circulating only one pulse sent by the first stage bistable element,
A control signal generation circuit, wherein a control signal is generated by extracting an output of a bistable element specified in advance. 2. The control signal generation circuit according to claim 1, wherein the output is cleared when a reset signal is applied, the output of the OR means is counted from an initial value when a load pulse is applied, and a carry is sent when a predetermined count value is reached. Counting means and a path switching means, wherein the path switching means outputs the output of the n-th stage bistable element when the carry is not applied, and the m-th stage (n> m when the carry is applied). 2. The control signal generating circuit according to claim 1, wherein an output of a bistable element (positive integer) is added to said OR means to switch a cycle of a generated control signal. 3. The switch means for sending the output of a bistable element selected according to the applied state of the carry to the logic means, wherein the path switching means is turned off when the carry is applied. Switching means for applying the output of the bistable element of the stage to the selector and turning off the input control means provided on the input side of the bistable element of the (m + 1) stage; 3. The control signal generation circuit according to claim 2, wherein the outputs of the bistable elements from the (m + 1) th stage to the nth stage are set to "0".