CN109995358B - State holding and clearing circuit and working circuit - Google Patents
State holding and clearing circuit and working circuit Download PDFInfo
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- CN109995358B CN109995358B CN201910188434.1A CN201910188434A CN109995358B CN 109995358 B CN109995358 B CN 109995358B CN 201910188434 A CN201910188434 A CN 201910188434A CN 109995358 B CN109995358 B CN 109995358B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
- H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The present invention relates to a state holding and clearing circuit and an operating circuit. The state maintaining and clearing circuit is applied to a state generating circuit and comprises an AND gate circuit, a one-way conduction switch and a reset circuit. The first input end of the AND gate circuit is connected with the output end of the state generating circuit, and the first input end of the AND gate circuit is used for receiving the state signal generated by the state generating circuit; the first input end of the AND gate circuit is connected with the output end of the one-way conduction switch, and the output end of the AND gate circuit is connected with the input end of the one-way conduction switch; the second input end of the AND gate circuit is used for being connected with a power supply and receiving a high level provided by the power supply; and the second input end of the AND gate circuit is connected with the reset circuit, the reset circuit is used for providing a reset signal to the second input end of the AND gate circuit, and the reset signal is used for reducing the high level provided by the power supply to the second input end of the AND gate circuit. The invention does not need to design software programming and use a processor, and has simple modes of keeping the state signal and clearing the state signal.
Description
Technical Field
The present invention relates to the field of electronic circuits, and more particularly, to a state holding and clearing circuit and an operating circuit.
Background
When the electronic device or the system fails in the operation process or the input quantity (such as voltage, current, temperature, frequency, power and the like) reaches a preset value, the electronic device or the system reports a reminding signal to the control center, so that the control center performs corresponding processing according to the reminding signal, for example, the operation of the electronic device at the rear stage is controlled. However, when the reminder is a short-time pulse signal, the control center can easily ignore the reminder or act as an interference signal, and the reminder is cleared without performing corresponding processing. For example, when a fault occurs in an electronic device or system, an alarm signal is sent to the control center, but due to the fault, the electronic device or system cannot continuously send the alarm signal to the control center, so that the control center easily ignores the alarm signal and does not timely handle the fault of the electronic device or system.
Currently, the state of the alert signal may be maintained by using an interrupt triggering manner to alert a processor such as a microprocessor Unit (MCU) to perform corresponding processing, and the alert signal is cleared after the MCU finishes processing. However, this method is generally implemented by a processor such as an MCU executing software programming, and the software programming design is complicated, and the processor such as the MCU is also required, so that the ways of holding the reminder signal and clearing the reminder signal are complicated.
Disclosure of Invention
In view of the above, it is necessary to provide a state holding and clearing circuit and an operating circuit to solve the problems of the prior art that additional controllers and software programming are required, the manner of holding the reminder signal and clearing the reminder signal is complicated.
A state keeping and clearing circuit is applied to a state generating circuit and comprises an AND gate circuit, a one-way conduction switch and a reset circuit;
the first input end of the AND gate circuit is connected with the output end of the state generating circuit and used for receiving the state signal generated by the state generating circuit;
the first input end of the AND gate circuit is connected with the output end of the one-way conduction switch, and the output end of the AND gate circuit is connected with the input end of the one-way conduction switch;
the second input end of the AND gate circuit is used for being connected with a power supply to receive a high level provided by the power supply;
the second input end of the AND gate circuit is connected with the reset circuit, the reset circuit is used for providing a reset signal to the second input end of the AND gate circuit, and the reset signal is used for reducing the high level provided by the power supply to the second input end of the AND gate circuit.
In one embodiment, the unidirectional conducting switch comprises a first transistor;
the base electrode of the first transistor is connected with the output end of the AND gate circuit;
the collector of the first transistor is used for being connected with the power supply;
and the emitter of the first transistor is connected with the first input end of the AND circuit.
In one embodiment, the unidirectional conducting switch comprises a diode;
the anode of the diode is connected with the output end of the AND gate circuit;
and the cathode of the diode is connected with the first input end of the AND circuit.
In one embodiment, the device comprises a first current limiting resistor;
the output end of the state generating circuit is connected with the first input end of the AND gate circuit through the first current limiting resistor.
In one embodiment, the reset circuit includes a controller, an output terminal of the controller is connected to the second input terminal of the and circuit, and the controller is configured to provide a reset signal to the second input terminal of the and circuit.
In one embodiment, the reset circuit further comprises a controlled switch;
the controlled end of the controlled switch is connected with the output end of the controller;
the first controlled switch end of the controlled switch is used for being connected with the power supply and the second input end of the AND circuit;
and the second controlled switch end of the controlled switch is used for grounding.
In one embodiment, the reset circuit comprises a manual switch and a controlled switch;
the first manual switch end of the manual switch is used for being connected with the power supply;
the second manual switch end of the manual switch is connected with the controlled end of the controlled switch;
the first controlled switch end of the controlled switch is used for being connected with the power supply and the second input end of the AND circuit;
and the second controlled switch end of the controlled switch is used for grounding.
In one embodiment, the controlled switch comprises a second transistor;
the base electrode of the second transistor is the controlled end of the controlled switch;
the collector of the second transistor is a first controlled switch end of the controlled switch;
the emitter of the second transistor is a second controlled switch terminal of the controlled switch.
In one embodiment, the reset circuit further includes a reset switch, the reset circuit further includes a relay, an input end of the relay is connected to an output end of the controller, an output end of the relay is connected to the second input end of the and circuit, and the controller is configured to control the relay to be closed when receiving the reset signal.
An operating circuit comprising a state generating circuit and a state holding and clearing circuit as described in any of the above embodiments.
In the state holding and clearing circuit and the working circuit, when the first input end and the second input end of the and gate circuit both input high levels, the output end of the and gate circuit outputs high levels; when the first input end or the second input end of the AND gate circuit inputs low level, the output end of the AND gate circuit outputs low level. Based on this, when the state generating circuit generates a transient state signal and the reset circuit does not provide the reset signal to the second input end of the and circuit, the and circuit outputs a high level which is the same as the state signal according to the state generating circuit and the high level provided by the power supply; when the state generating circuit does not continuously generate the state signal, the one-way conduction switch is conducted due to forward input, the output end of the AND gate circuit provides a high level to the first input end, and the AND gate circuit continuously outputs the high level which is the same as the state signal according to the power supply and the high level provided by the output end of the AND gate circuit, so that the state signal is continuously output; in addition, when the status signal does not need to be held, the reset circuit provides a reset signal to the second input terminal, and the reset signal reduces the high level provided by the power supply to the second input terminal of the and circuit, so that the output terminal of the and circuit is at the low level, and the status signal is cleared. Therefore, the invention does not need to design software programming and use a processor, and the mode of keeping the state signal and clearing the state signal is simple.
Drawings
FIG. 1 is a schematic diagram of a state holding and clearing circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram of the status signal, the reset signal, and the output signal of the status holding and clearing circuit according to the embodiment of the present invention;
FIG. 3 is a circuit diagram of a state hold and clear circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a state hold and clear circuit in accordance with another embodiment of the present invention;
FIG. 5 is a circuit diagram of a state hold and clear circuit according to yet another embodiment of the present invention;
FIG. 6 is a circuit diagram of a state hold and clear circuit according to yet another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below by way of embodiments with reference to the accompanying drawings.
The embodiment of the invention provides a state holding and clearing circuit.
FIG. 1 is a diagram of a state hold and clear circuit. As shown in fig. 1, the state holding and clearing circuit applied to the state generating circuit 100 includes an and circuit U1, a unidirectional conducting switch 201, and a reset circuit 202.
A first input terminal of the and circuit U1 is connected to the output terminal of the state generating circuit 100, and a first input terminal of the and circuit U1 is configured to receive the state signal generated by the state generating circuit 100.
Generally, as shown in fig. 2, the state generating circuit 100 outputs a low level at the power-on initial state, then the output changes from the low level to the high level, and after the output continues to output the high level for a while, the output changes from the high level to the low level again, and keeps outputting the low level all the time. When the state generating circuit generates a state signal triggered by an external or internal factor, for example, a fault occurs inside the circuit, or a current input (such as voltage, current, temperature, frequency, power, etc.) reaches a predetermined value, the state generating circuit generates a state signal, and the state signal generated by the state generating circuit 100 can be used to control the operation of the state post-stage circuit 400. Taking the post-state circuit 400 as an alarm circuit, the state generating circuit 100 outputs a low level when no fault occurs, and generates a transient alarm signal when a fault occurs, and the alarm signal can be used to trigger the alarm circuit to issue an alarm prompt. Taking the state generating circuit 100 as a temperature sensor and the state post-stage circuit 400 as a heating circuit as an example, when the temperature sensor detects that the current temperature reaches a predetermined value, the state generating circuit 100 generates a temperature reaching signal, and the temperature reaching signal can be used for triggering the heating circuit to stop operating.
The first input end of the and-gate circuit U1 is connected to the output end of the unidirectional conducting switch 201, and the output end of the and-gate circuit U1 is connected to the input end of the unidirectional conducting switch 201.
In one embodiment, the unidirectional conducting switch 201 has the characteristic of unidirectional conducting. Specifically, an input end of the unidirectional conducting switch 201 is connected to an output end of the and circuit U1, and an output end of the unidirectional conducting switch 201 is connected to a first input end of the and circuit U1. In one embodiment, the unidirectional on switch 201 turns on the forward input and turns off the reverse input. When the unidirectional conducting switch 201 is turned on by the forward input, the output terminal of the and circuit U1 may control the input of the first input terminal of the and circuit U1, for example, when the output terminal of the and circuit U1 outputs a high level, the input of the first input terminal of the and circuit U1 is a high level. When the one-way conduction switch 201 is turned off by the inverted input, the state signal generated by the state generating circuit 100 cannot be directly supplied to the output terminal of the and circuit U1.
A second input terminal of the and circuit U1 is for connection with the power supply 300 to receive a high level provided by the power supply 300.
In one embodiment, the power supply 300 is further configured to provide an operating voltage for the and circuit U1, so that the and circuit U1 can operate normally.
The second input terminal of the and circuit U1 is connected to the reset circuit 202, the reset circuit 202 is configured to provide a reset signal to the second input terminal of the and circuit U1, and the reset signal is configured to lower the high level provided by the power supply 300 to the second input terminal of the and circuit U1.
Specifically, as shown in fig. 2, when the state generating circuit 100 generates a short-time state signal, for example, 15 ns, 20 ns, 25 ns, 30 ns, 35 ns, 40 ns, 45 ns, 50 ns, etc., and the reset circuit 202 does not supply the low-level reset signal to the second input terminal of the and circuit U1, the and circuit U1 outputs the same high level as the state signal according to the high levels supplied by the state generating circuit 100 and the power supply 300, and the output terminal of the and circuit U1. When the state generating circuit 100 does not generate the state signal continuously, the one-way conducting switch 201 is turned on due to the positive input, the output terminal of the and circuit U1 provides the high level to the first input terminal, and at this time, the and circuit U1 continues to output the same high level as the state signal according to the power supply 300 and the high level provided by the output terminal of the and circuit U1, so as to keep outputting the state signal continuously.
In addition, when the status signal does not need to be held, the reset circuit 202 may provide a low-level reset signal to the second input terminal of the and circuit U1, and the reset signal lowers the high level provided by the power supply 300 to the second input terminal of the and circuit U1, so that the output terminal of the and circuit U1 is at a low level, thereby clearing the status signal.
Referring to fig. 3, in one embodiment, the one-way conducting switch 201 includes a first transistor Q1. The base of the first transistor Q1 is connected to the output terminal of the and circuit U1, the collector of the first transistor Q1 is used for connecting to the power supply 300, and the emitter of the first transistor Q1 is connected to the first input terminal of the and circuit U1.
In fig. 3, the first transistor Q1 is an NPN transistor, for example, and the operation principle of the unidirectional conducting switch 201 is explained. It should be noted that the NPN transistor is not limited to the unidirectional conducting switch 201, and may be adjusted according to the type of the first transistor Q1.
As shown in fig. 3, when the state generating circuit 100 generates the state signal, the first transistor Q1 is turned off, so that the first input terminal of the and circuit U1 receives a high level of the state signal. When the control signal of the base of the first transistor Q1 output by the output end of the and circuit U1 is at a high level, the first transistor Q1 is turned on, and the high level output by the output end of the and circuit U1 is transmitted to the first input end of the and circuit U1 through the emitter of the first transistor Q1, so that the input of the first input end of the and circuit U1 is at a high level. In this way, the first transistor Q1 can maintain the high input of the first input terminal of the and circuit U1.
In addition, since the first transistor Q1 is turned off in the reverse input direction, the state signal generated by the state generating circuit 100 cannot be directly supplied to the output terminal of the and circuit U1, that is, the output terminal of the and circuit U1 is not directly controlled by the state generating circuit 100. In this way, the reset circuit 202 provides the reset signal to the second input terminal of the and circuit U1, so that the output terminal of the and circuit U1 can be changed from the high level to the low level, thereby implementing the reset function.
Referring to fig. 4, in one embodiment, the one-way conducting switch 201 includes a diode D1. The anode of the diode D1 is connected with the output end of the AND circuit U1, and the cathode of the diode D1 is connected with the first input end of the AND circuit U1.
When the state generating circuit 100 generates the state signal, the diode D1 is turned off in the reverse direction, so that the first input terminal of the and circuit U1 receives the high level of the state signal. When the output end of the and circuit U1 outputs a high level, the diode D1 is turned on in the forward direction, so that the first input end of the and circuit U1 receives the high level output by the output end of the and circuit U1. In this way, the diode D1 can maintain the high input of the first input terminal of the and circuit U1.
In addition, since the reverse input of the diode D1 is turned off, the state signal generated by the state generating circuit 100 cannot be directly provided to the output terminal of the and circuit U1, that is, the output terminal of the and circuit U1 is not directly controlled by the state generating circuit 100. In this way, by providing the reset signal to the second input terminal of the and circuit U1 through the reset circuit 202, the output terminal of the and circuit U1 can be changed from the high level to the low level, thereby implementing the reset function.
Referring to fig. 3 and 4, in one embodiment, the state holding and clearing circuit includes a first current limiting resistor R1. The output terminal of the state generating circuit 100 is connected to the first input terminal of the and circuit U1 through the first current limiting resistor R1. The state signal generated by the state generating circuit 100 is input to the first input terminal of the and circuit U1 through the first current limiting resistor R1, so as to protect the and circuit U1 and prevent overcurrent.
Referring to fig. 5, in one embodiment, the reset circuit 202 includes a controller 2021. An output terminal of the controller 2021 is connected to a second input terminal of the and circuit U1, and the controller 2021 is configured to provide a reset signal to the second input terminal of the and circuit U1.
The controller 2021 may directly input the reset signal to the second input terminal of the and circuit U1, and the reset signal lowers the high level supplied by the power supply 300 to the second input terminal of the and circuit U1, so that the second input terminal of the and circuit U1 inputs the low level and the output terminal of the and circuit U1 outputs the low level, thereby clearing the status signal.
With continued reference to fig. 5, in one embodiment, the reset circuit 202 further includes a controlled switch 2022. The controlled end of the controlled switch 2022 is connected to the output end of the controller 2021; a first controlled switch end of the controlled switch 2022 is used for being connected with the power supply 300 and a second input end of the and circuit U1; the second controlled switch terminal of the controlled switch 2022 is used for ground.
Specifically, the controller 2021 inputs a low-level reset signal to the second input terminal of the and circuit U1 by inputting a high level to the controlled switch 2022. When the controlled terminal of the controlled switch 2022 receives the high level output by the controller 2021, the first controlled switch terminal and the second controlled switch terminal thereof are turned on, the output terminal of the reset circuit 202 is pulled down to the ground signal, and the reset signal is at the low level, so as to lower the high level provided by the power supply 300 to the second input terminal of the and circuit U1, so that the output terminal of the and circuit U1 outputs the low level, thereby clearing the status signal. When the controlled terminal of the controlled switch 2022 does not receive the high level output by the controller 2021, the first controlled switch terminal and the second controlled switch terminal are not turned on, at this time, the reset signal is at a high level and cannot reduce the high level provided by the power supply 300 to the second input terminal of the and circuit U1, and the output terminal of the and circuit U1 outputs the high level, thereby maintaining the state signal.
Referring to fig. 6, in one embodiment, the reset circuit 202 includes a manual switch K1 and a controlled switch 2022, a first manual switch end of the manual switch K1 is used for connecting with the power source 300, and a second manual switch end of the manual switch K1 is connected with a controlled end of the controlled switch 2022; a first controlled switch end of the controlled switch 2022 is used for being connected with the power supply 300 and a second input end of the and circuit U1; the second controlled switch terminal of the controlled switch 2022 is used for ground.
When the manual switch K1 is closed, the power supply 300 inputs a high level to the controlled terminal of the controlled switch 2022. When the controlled terminal of the controlled switch 2022 receives the high level output by the power supply 300, the first controlled switch terminal and the second controlled switch terminal thereof are turned on, the output terminal of the reset circuit 202 is pulled down to the ground signal, and the reset signal is at the low level, so as to lower the high level provided by the power supply 300 to the second input terminal of the and circuit U1, and the output terminal of the and circuit U1 outputs the low level, thereby clearing the status signal. When the manual switch K1 is turned off, the first controlled switch end and the second controlled switch end are not turned on, at this time, the reset signal is at a high level and cannot lower the high level provided by the power supply 300 to the second input end of the and circuit U1, and the output end of the and circuit U1 outputs the high level, so that the state signal is maintained.
With continued reference to fig. 5 and 6, in one embodiment, the controlled switch 2022 includes a second transistor Q2. The base of the second transistor Q2 is the controlled end of the controlled switch 2022; the collector of the second transistor Q2 is a first controlled switch terminal of the controlled switch 2022; the emitter of the second transistor Q2 is the second controlled switch terminal of the controlled switch 2022.
In fig. 5 and fig. 6, the second transistor Q2 is an NPN transistor as an example, and the operating principle of the controlled switch 2022 is explained. It should be noted that the NPN transistor is not limited to the controlled switch 2022, and may be adjusted according to the type of the second transistor Q2.
When the second transistor Q2 does not receive the high level provided by the controller 2021 or the power supply 300, the second transistor Q2 is turned off, and at this time, the reset signal is at a high level and cannot lower the high level provided by the power supply 300 to the second input terminal of the and circuit U1, and the output terminal of the and circuit U1 outputs the high level, thereby maintaining the state signal. When the second transistor Q2 receives the high level provided by the controller 2021 or the power supply 300, the control signal at the base of the second transistor Q2 is at the high level, the second transistor Q2 is turned on, the output terminal of the reset circuit 202 is pulled down to the ground signal, and at this time, the reset signal is at the low level, so as to reduce the high level provided by the power supply 300 to the second input terminal of the and circuit U1, and the output terminal of the and circuit U1 outputs the low level, so as to clear the status signal.
With continued reference to fig. 5 and 6, in one embodiment, the state retention and clearing circuit includes a pull-up resistor R2. The power supply 300 is connected to the collector of the second transistor Q2 and the second input terminal of the and circuit U1 through a pull-up resistor R2.
The power supply 300 is connected to the collector of the second transistor Q2 through the pull-up resistor R2, so that when the controller 2021 or the power supply 300 provides a high level to the base of the second transistor Q2 and the second transistor Q2 is turned on, the pull-up resistor R2 protects the second transistor Q2 from overcurrent. The power supply 300 is connected to the second input terminal of the and circuit U1 through the pull-up resistor R2, so that when the second transistor Q2 is turned off and the power supply 300 provides a high level to the second input terminal of the and circuit U1, the pull-up resistor R2 protects the and circuit U1 from overcurrent.
With continued reference to fig. 5 and 6, in one embodiment, the state holding and clearing circuit includes a second current limiting resistor R3. The base of the second transistor Q2 is connected to the controller 2021 or the manual switch K1 through a second current limiting resistor R3. Thus, when the controller 2021 or the power supply 300 provides a high level to the base of the second transistor Q2, the second transistor Q2 is turned on, and the second current-limiting resistor R3 protects the second transistor Q2 from overcurrent.
In one of the embodiments, the controlled switch 2022 comprises an electronic switch. The controlled terminal of the electronic switch controls the first controlled switch terminal and the second controlled switch terminal to be turned on or off according to the reset signal provided by the controller 2021 or the power supply 300, so as to control whether the controller 2021 or the manual switch K1 provides the reset signal to the second input terminal of the and circuit U1.
In one embodiment, the reset circuit 202 further comprises a relay, an input terminal of the relay is connected to an output terminal of the controller 2021, an output terminal of the relay 2021 is connected to the second input terminal of the and circuit U1, and the controller 2021 is configured to control the relay to close when receiving the reset signal.
When the relay does not receive the reset signal, the controller 2021 controls the relay to be turned off, the power supply 300 provides a high level to the second input terminal of the and circuit U1, and the output terminal of the and circuit U1 outputs the high level, so that the status signal is maintained. When the relay receives the reset signal, the controller 2021 controls the relay to close, and the reset signal lowers the high level supplied from the power supply 300 to the second input terminal of the and circuit U1, so that the second input terminal of the and circuit U1 inputs the low level and the output terminal of the and circuit U1 outputs the low level, thereby clearing the status signal.
Referring to fig. 6, an embodiment of the invention further provides a working circuit. The operation circuit includes the state generating circuit 100 and the state holding and clearing circuit as described in any of the above embodiments.
In one embodiment, the operating circuit further includes a state post-stage circuit 400 of the state generating circuit 100, and the state signal generated by the state generating circuit 100 can be used to control the operation of the state post-stage circuit 400.
In the state maintaining and clearing circuit and the working circuit, when the first input end and the second input end of the and gate circuit U1 both input high levels, the output end of the and gate circuit U1 outputs high levels; when the first input end or the second input end of the and circuit U1 inputs a low level, the output end of the and circuit U1 outputs a low level. Based on this, when the state generating circuit 100 generates a transient state signal and the reset circuit 202 does not provide the reset signal to the second input terminal of the and circuit U1, the and circuit U1 outputs a high level same as the state signal according to the high level provided by the state generating circuit 100 and the power supply 300; when the state generating circuit 100 does not continuously generate the state signal, the one-way conduction switch 201 is turned on due to the positive input, the output end of the and circuit U1 provides a high level to the first input end, and at this time, the and circuit U1 continuously outputs a high level the same as the state signal according to the power supply 300 and the high level provided by the output end of the and circuit U1, so as to keep continuously outputting the state signal; in addition, when the status signal is not required to be held, the reset circuit 202 may provide a reset signal to the second input terminal, and the reset signal lowers the high level provided by the power supply 300 to the second input terminal of the and circuit U1, so that the output terminal of the and circuit U1 is at the low level, thereby clearing the status signal. Therefore, the invention does not need to design software programming and use a processor, and the mode of keeping the state signal and clearing the state signal is simple.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features. The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the spirit of the invention, which falls within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A state keeping and clearing circuit is applied to a state generating circuit and is characterized by comprising an AND gate circuit, a one-way conduction switch and a reset circuit;
the first input end of the AND gate circuit is connected with the output end of the state generating circuit, and the first input end of the AND gate circuit is used for receiving the state signal generated by the state generating circuit;
the first input end of the AND gate circuit is connected with the output end of the one-way conduction switch, and the output end of the AND gate circuit is connected with the input end of the one-way conduction switch;
the second input end of the AND gate circuit is used for being connected with a power supply to receive a high level provided by the power supply;
the second input end of the AND gate circuit is connected with the reset circuit, the reset circuit is used for providing a reset signal to the second input end of the AND gate circuit, and the reset signal is used for reducing the high level provided by the power supply to the second input end of the AND gate circuit.
2. The state hold and clear circuit of claim 1, wherein the unidirectional conducting switch comprises a first transistor;
the base electrode of the first transistor is connected with the output end of the AND gate circuit;
the collector of the first transistor is used for being connected with the power supply;
and the emitter of the first transistor is connected with the first input end of the AND circuit.
3. The state-hold and clear circuit of claim 1, wherein the unidirectional conducting switch comprises a diode;
the anode of the diode is connected with the output end of the AND circuit;
and the cathode of the diode is connected with the first input end of the AND circuit.
4. The state holding and clearing circuit according to claim 2 or 3, comprising a first current limiting resistor;
the output end of the state generating circuit is connected with the first input end of the AND gate circuit through the first current limiting resistor.
5. The state hold and clear circuit of claim 1, wherein the reset circuit comprises a controller, an output of the controller being coupled to the second input of the and circuit, the controller being configured to provide a reset signal to the second input of the and circuit.
6. The state hold and clear circuit of claim 5, wherein the reset circuit further comprises a controlled switch;
the controlled end of the controlled switch is connected with the output end of the controller;
the first controlled switch end of the controlled switch is used for being connected with the power supply and the second input end of the AND circuit;
the second controlled switch terminal of the controlled switch is used for grounding.
7. The state-hold and clear circuit of claim 1, wherein the reset circuit comprises a manual switch and a controlled switch;
the first manual switch end of the manual switch is used for being connected with the power supply;
the second manual switch end of the manual switch is connected with the controlled end of the controlled switch;
the first controlled switch end of the controlled switch is used for being connected with the power supply and the second input end of the AND circuit;
and the second controlled switch end of the controlled switch is used for grounding.
8. The state hold and clear circuit of claim 6 or 7, wherein the controlled switch comprises a second transistor;
the base electrode of the second transistor is the controlled end of the controlled switch;
the collector of the second transistor is a first controlled switch end of the controlled switch;
the emitter of the second transistor is a second controlled switch terminal of the controlled switch.
9. The status holding and clearing circuit of claim 5, wherein said reset circuit further comprises a relay having an input connected to an output of said controller, an output connected to a second input of said AND gate, said controller configured to control said relay to close upon receiving said reset signal.
10. An operating circuit comprising a state generating circuit and a state holding and clearing circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910188434.1A CN109995358B (en) | 2019-03-13 | 2019-03-13 | State holding and clearing circuit and working circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910188434.1A CN109995358B (en) | 2019-03-13 | 2019-03-13 | State holding and clearing circuit and working circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109995358A CN109995358A (en) | 2019-07-09 |
| CN109995358B true CN109995358B (en) | 2022-12-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910188434.1A Active CN109995358B (en) | 2019-03-13 | 2019-03-13 | State holding and clearing circuit and working circuit |
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| JPH09205349A (en) * | 1996-01-26 | 1997-08-05 | Matsushita Electric Ind Co Ltd | Pulse width selection signal output device |
| JPH1114653A (en) * | 1997-06-26 | 1999-01-22 | Nippon Signal Co Ltd:The | Signal-monitoring circuit and rotation stop sensor using it |
| JP2001196911A (en) * | 2000-01-14 | 2001-07-19 | Sadao Nakano | Timer switch |
| CN101807905A (en) * | 2010-02-11 | 2010-08-18 | 西安能讯微电子有限公司 | Drive circuit of deplete semiconductor switching element and drive method thereof |
| CN105162441A (en) * | 2015-09-25 | 2015-12-16 | 中国电子科技集团公司第二十四研究所 | High-speed low-power-consumption dynamic comparator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5910793B2 (en) * | 2013-04-26 | 2016-04-27 | 株式会社オートネットワーク技術研究所 | Fail safe circuit |
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| JPH09205349A (en) * | 1996-01-26 | 1997-08-05 | Matsushita Electric Ind Co Ltd | Pulse width selection signal output device |
| JPH1114653A (en) * | 1997-06-26 | 1999-01-22 | Nippon Signal Co Ltd:The | Signal-monitoring circuit and rotation stop sensor using it |
| JP2001196911A (en) * | 2000-01-14 | 2001-07-19 | Sadao Nakano | Timer switch |
| CN101807905A (en) * | 2010-02-11 | 2010-08-18 | 西安能讯微电子有限公司 | Drive circuit of deplete semiconductor switching element and drive method thereof |
| CN105162441A (en) * | 2015-09-25 | 2015-12-16 | 中国电子科技集团公司第二十四研究所 | High-speed low-power-consumption dynamic comparator |
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| CN109995358A (en) | 2019-07-09 |
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