JPS6320023B2 - - Google Patents

Info

Publication number
JPS6320023B2
JPS6320023B2 JP53124904A JP12490478A JPS6320023B2 JP S6320023 B2 JPS6320023 B2 JP S6320023B2 JP 53124904 A JP53124904 A JP 53124904A JP 12490478 A JP12490478 A JP 12490478A JP S6320023 B2 JPS6320023 B2 JP S6320023B2
Authority
JP
Japan
Prior art keywords
region
mos transistor
potential
depletion layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53124904A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5552267A (en
Inventor
Shinji Morozumi
Tatsuji Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP12490478A priority Critical patent/JPS5552267A/ja
Publication of JPS5552267A publication Critical patent/JPS5552267A/ja
Publication of JPS6320023B2 publication Critical patent/JPS6320023B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/857—Complementary IGFETs, e.g. CMOS comprising an N-type well but not a P-type well

Landscapes

  • Semiconductor Memories (AREA)
JP12490478A 1978-10-11 1978-10-11 Semiconductor meomory Granted JPS5552267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12490478A JPS5552267A (en) 1978-10-11 1978-10-11 Semiconductor meomory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12490478A JPS5552267A (en) 1978-10-11 1978-10-11 Semiconductor meomory

Publications (2)

Publication Number Publication Date
JPS5552267A JPS5552267A (en) 1980-04-16
JPS6320023B2 true JPS6320023B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-04-26

Family

ID=14896978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12490478A Granted JPS5552267A (en) 1978-10-11 1978-10-11 Semiconductor meomory

Country Status (1)

Country Link
JP (1) JPS5552267A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6088458A (ja) * 1983-10-20 1985-05-18 Toshiba Corp 半導体記憶装置
US4868628A (en) * 1984-08-22 1989-09-19 Signetics Corporation CMOS RAM with merged bipolar transistor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927110B2 (ja) * 1975-08-22 1984-07-03 セイコーエプソン株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS5552267A (en) 1980-04-16

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