JPS63196058A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the thickness of junction part with an SiO2 film covering a groove for preventing any exfoliation and contact with Si electrode as well as charging up from occurring by a method wherein, after removing a part of diffused source film laid between a buried Si and an SiO2 film from the surface side of a substrate, another SiO2 film is formed on the surface of buried Si by thermal oxidation. CONSTITUTION:In order to form an insulating isolation region composed of a buried groove structure comprising a groove 4 with inner surface thereof covered with silicon dioxide SiO2 film 5 further filled with silicon Si 6, a diffused source film 8 comprising Si and a material in higher etching rate than that of Si and SiO2 to be a conductivity type impurity diffused source to Si is laid between the SiO2 film 5 and the buried Si 6 and after removing a part of diffused source film 6 from the surface side of substrate 1, another SiO2 film 7 is formed on the surface of buried Si 6 by thermal oxidation. Through these procedures, the buried Si 6 is provided with conductivity while the thickness of junction part of the SiO2 film 7 on Si 6 with the SiO2 film 5 covering the groove 4 can be increased.

Description

[Detailed Description of the Invention] [Summary] In a semiconductor device, the inner surface is made of silicon dioxide (Si02
) In the formation of the insulating m region of the buried trench structure in which silicon (St) is buried in the trench covered with a film, a diffusion layer made of a material that serves as a conductivity type impurity diffusion source for Si and has a higher etching rate than St and 5i02 is used. Source film above s 102 Ij! After removing a part of the diffusion source film from the surface side of the substrate, a 5i02 film is formed on the surface of the buried St by thermal oxidation, thereby increasing the conductivity of the buried Si. 5i0211 on embedded Si with
! The thickness of the joint with the SiOzM covering the groove is increased.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an insulating isolation region of a buried trench structure.

In a semiconductor device in which an integrated circuit is incorporated in a semiconductor substrate, an insulating isolation region for element isolation is formed in the substrate.

As integration becomes higher, there is a tendency for a trench-buried structure (so-called trench structure) to be adopted for this insulating isolation region, which reduces the area occupied by the substrate.

[Conventional technology]

An example of a conventional method for forming an insulating isolation region in a trench-buried structure is as follows.
As shown in the step-by-step side view of FIG.

That is, in FIG. 2, first, see FIG. C (a), a 5i0
2 film 2 and silicon nitride (SiN) II! 3 are sequentially formed and patterned to remove a portion of the region to be an insulating isolation region.

Next, see [Illustration price], y! A groove 4 is formed in the substrate 1 by etching using 3 and 2 as masks, and a 5t021 odor 5 is formed on the inner surface of the groove 4 by thermal oxidation.

Next, as shown in the figure (see C1), polycrystalline silicon (poly-Si) is deposited as thickly as 6a so as to sufficiently fill the groove 4.

Next (see figure (d)), bouncing is performed until the poly-Si on the SiN film 3 is removed to form a buried Si 6.

In this polishing, the SiN film 3 serves as a stopper.

Note that instead of the borishing, a method may be used in which a resist is applied onto poly-Si and etched back by dry etching.

Next, a 5i02 film 7 is formed on the surface of the buried Si6 by oxidation to complete an insulating isolation region.Both ends of the 5i02 film 7 are bonded to the 5i02 film 5, and the buried Si6 is bonded to the 5i02 film 5. surrounded by both.

After this, if necessary, 5iNll[3 is removed, and a semiconductor device is completed through an element formation process, a wiring formation process, etc.

[Problem that the invention seeks to solve]

By the way, the insulating isolation region formed by the above method has the following problems [see Figure 3]: (1) Because the buried Si6 has high insulating properties, it is easily charged due to stress in subsequent steps. may be uploaded,
The charged-up portion is likely to cause channel leakage as indicated by arrow 11.

■ 5i02117 has a thinner joint with 5i02115, so it may peel off as shown at 12 due to stress in later steps, and also may cause misalignment of the contact hole 14 when forming the electrode 13. At this time, the electrode 13 may come into contact with the buried Si 6.

(Means for Solving the Problems) The above problems are solved by the step of forming a trench whose inner surface is covered with 5i02111 in the semiconductor substrate, and which acts as a conductivity type impurity diffusion source for St and has a lower etching rate than St and 5i02. The diffusion source film made of a material with high s i0
2, a step of depositing Si on the deposited liquid groove of the diffusion source film, and a step of depositing Si on the deposited Si layer, and depositing Si on the diffusion source film interposed between the buried Si and the 5i02 film. By the manufacturing method of the present invention, which includes the step of removing a part of the film from the surface side of the substrate and then forming 5i02111 on the surface of the buried Si by thermal oxidation to form an insulating isolation region of a trench buried structure. resolved.

[Effect]

Due to the heating during the thermal oxidation, impurities are diffused from the diffusion source film, and the buried Si buried in the trench becomes conductive. This conductivity prevents the charge-up mentioned above and eliminates the fear of channel leakage.

Further, by removing the above-described portion of the diffusion source film, the 5i02111 on the buried St fills the removed portion during its formation, so that the thickness of the junction with the 5i02 film covering the trench increases. This increase is due to the peeling and embedding S
i prevent contact with the electrode.

〔Example〕

Examples of the method of the present invention will be described below with reference to step-by-step side views of FIG. The same reference numerals refer to the same objects throughout the design.

In the figure, first [see figure (a)], a SiO2 film 5 is
The process up to the formation of

Next, a diffusion source film 8 made of a material that serves as a conductive type impurity diffusion source for Si and has a higher etching rate than Si and SiO2 is deposited over the entire surface. For example, phosphorus glass (PSG) containing phosphorus (P) as an impurity or boron glass (BPSG) containing boron (B) as an impurity is used as this material, and the deposition is carried out by ordinary chemical vapor deposition (CVD). It can be done.

Next, [see Figure (C)], the conventional example in Figure 2 (C) (d
) in the same manner as shown in Diffusion Source II! A poly-Si embedded Si 6 is formed to fill the groove 4 where the No. 8 is deposited.

With this formation, the diffusion source 1llI8 becomes 5tozl
l! The part above 2 is removed and embedded Si6 and 5i02
1 odor 5 remains.

Then (see figure (d)), 5iOz was applied to the surface of the embedded Si6.
As a pretreatment for thermal oxidation that forms odor 7, dilute hydrofluoric acid (H
F) Perform cleaning with liquid, then St and 5i0
The diffusion source film 8 having an etching rate higher than 2 is etched from the surface side of the substrate 10, and the portion indicated by 9 is removed.

Next (see Figure (e)), a 5i02 film 7 is formed on the surface of the buried Si 6 by thermal oxidation to complete a desired insulation isolation region.

In this thermal oxidation, the side surface of the buried Si6 exposed in the removed portion 9 also contributes to the formation of the 5i02 film 7, so the 5i02 film 8 fills the removed portion 9 and reduces the thickness of the joint with the 5i02 film 5. It is thicker (thicker than that of the conventional example). Also, conductivity type impurities such as P are diffused from the diffusion source yI8 into the buried Si6, and the buried S
i6 becomes conductive.

The subsequent steps leading to the completion of the semiconductor device are the same as before.

Note that the dimensions of each part of the above-mentioned insulation isolation region are, for example, the size of the groove 4.
The width is 4~6μ, the depth is 3~5μ, 5i021
The thickness of 115 is 0.3 to 0.5 μm, and the thickness of 5i02 film 7 is 0.5 to 0.8 μm at the center and 0.3 to 0.5 at the ends.
The value is μ.

In the element isolation insulation region formed in this way, the buried Si
Since 6 is conductive, even if a charge is generated partially, the charge will not be accumulated but will be dissipated.
Charge-up that causes channel leakage no longer occurs. In addition, since the thickness of the joint between 5i021147 and 5i02115 is as thick as 0.3 to 0.5 μm as described above, the embedded Si6 electrode due to peeling or misalignment of the contact hole as described above. contact will no longer occur.

In the drawings of the above embodiment, the groove 4 has a V-shape, but it is easily understood that it may have another shape, such as a U-shape.

〔Effect of the invention〕

As explained above, according to the configuration of the present invention, the inner surface of the semiconductor device is 5 iOzll! In forming an insulating isolation region of a trench-buried structure in which Si is buried in a trench covered with
Along with making the embedded Si conductive, 5t02i* on the embedded St
5iO2y/! that covers the grooves! It is possible to increase the thickness of the junction with the 5i02 film, eliminate the fear of channel leakage in the insulation isolation region, and reduce the peeling of the 5i02 film.
This has the effect of preventing the embedded Si from coming into contact with other electrodes.

[Brief explanation of the drawing]

FIG. 1 is a step-by-step side view of an embodiment of the method of the present invention, FIG. 2 is a step-by-step side view of an example of a conventional method, and FIG. 3 is an explanatory diagram of problems. In the figure, 1 is the substrate, 2.5.7 is the 5i02 film, 3 is the SiN film, 4 is the groove, 6 is the buried 5is, 8 is the diffusion source film, 9 is the removed portion, 11 is the channel leak, 12 is the peeling, 13 is an electrode, and 14 is a contact hole. Inner Hizu Pregnancy - Archery Archery 5 Nomi-tei Koopuri 0 Process @Me 9 Side L She] 1L 1 (Ko

Claims (1)

[Claims] A step of forming a trench whose inner surface is covered with a silicon dioxide film in a semiconductor substrate, and a diffusion source film made of a material that serves as a conductive impurity diffusion source for silicon and has a higher etching rate than silicon and silicon dioxide. a step of depositing silicon on top of the diffusion source film, a step of burying silicon in the groove in which the diffusion source film is deposited, and a step of depositing silicon on the silicon dioxide film; and a step of depositing silicon on the silicon dioxide film; After removing a part of from the surface side of the substrate,
1. A method of manufacturing a semiconductor device, comprising the step of forming a silicon dioxide film on the surface of the buried silicon by thermal oxidation to form an insulating isolation region of a buried trench structure.