JPS63192747U - - Google Patents
Info
- Publication number
- JPS63192747U JPS63192747U JP8442787U JP8442787U JPS63192747U JP S63192747 U JPS63192747 U JP S63192747U JP 8442787 U JP8442787 U JP 8442787U JP 8442787 U JP8442787 U JP 8442787U JP S63192747 U JPS63192747 U JP S63192747U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- identification
- input buffer
- side input
- buffer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008929 regeneration Effects 0.000 claims description 4
- 238000011069 regeneration method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案による識別再生回路の実施例を
示す回路ブロツク図、第２図は識別再生回路の相
対位相変化に対するクロツク入力ＤＣバイアスの
動作範囲を示す図、第３図は、クロツク側入力バ
ツフア回路の周波数特性を示す図、第４図はクロ
ツク信号波形を示す図、第５図は従来の識別再生
回路の回路ブロツク図である。
１……データ側入力バツフア回路、２……直流
再生回路、３……クロツク側入力バツフア回路、
４……識別回路（Ｉ・Ｃ）、５……抵抗。
FIG. 1 is a circuit block diagram showing an embodiment of the identification and regeneration circuit according to the present invention, FIG. 2 is a diagram showing the operating range of the clock input DC bias with respect to the relative phase change of the identification and regeneration circuit, and FIG. 3 is a diagram showing the operating range of the clock input DC bias. FIG. 4 is a diagram showing the frequency characteristics of the buffer circuit, FIG. 4 is a diagram showing the clock signal waveform, and FIG. 5 is a circuit block diagram of a conventional identification and reproducing circuit. 1...Data side input buffer circuit, 2...DC regeneration circuit, 3...Clock side input buffer circuit,
4...Identification circuit (I/C), 5...Resistor.
Claims (1)
力が前記データ側入力バツフア回路出力に接続さ
れ、出力が前記識別回路のデータ信号入力端に接
続された直流再生回路と、クロツク側入力バツフ
ア回路と、前記クロツク側入力バツフア回路出力
と前記識別回路のクロツク入力端子の間に接続さ
れた抵抗とから構成したことを特徴とする識別再
生回路。 an identification circuit, a data side input buffer circuit, a DC regeneration circuit whose input is connected to the output of the data side input buffer circuit and whose output is connected to the data signal input end of the identification circuit, and a clock side input buffer circuit; An identification reproducing circuit comprising a resistor connected between the output of the clock side input buffer circuit and the clock input terminal of the identification circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987084427U JPH0641407Y2 (en) | 1987-05-29 | 1987-05-29 | Identification reproduction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987084427U JPH0641407Y2 (en) | 1987-05-29 | 1987-05-29 | Identification reproduction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63192747U true JPS63192747U (en) | 1988-12-12 |
| JPH0641407Y2 JPH0641407Y2 (en) | 1994-10-26 |
Family
ID=30938918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987084427U Expired - Lifetime JPH0641407Y2 (en) | 1987-05-29 | 1987-05-29 | Identification reproduction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0641407Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60204139A (en) * | 1984-03-28 | 1985-10-15 | Nec Corp | Timing circuit |
| JPS611150A (en) * | 1984-06-14 | 1986-01-07 | Fujitsu Ltd | Ringing preventing circuit |
-
1987
- 1987-05-29 JP JP1987084427U patent/JPH0641407Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60204139A (en) * | 1984-03-28 | 1985-10-15 | Nec Corp | Timing circuit |
| JPS611150A (en) * | 1984-06-14 | 1986-01-07 | Fujitsu Ltd | Ringing preventing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0641407Y2 (en) | 1994-10-26 |
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