JPS6317590B2 - - Google Patents
Info
- Publication number
- JPS6317590B2 JPS6317590B2 JP53107796A JP10779678A JPS6317590B2 JP S6317590 B2 JPS6317590 B2 JP S6317590B2 JP 53107796 A JP53107796 A JP 53107796A JP 10779678 A JP10779678 A JP 10779678A JP S6317590 B2 JPS6317590 B2 JP S6317590B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- wrapping
- warpage
- wrapped
- sided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10779678A JPS5537229A (en) | 1978-09-01 | 1978-09-01 | Lapping method of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10779678A JPS5537229A (en) | 1978-09-01 | 1978-09-01 | Lapping method of wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5537229A JPS5537229A (en) | 1980-03-15 |
| JPS6317590B2 true JPS6317590B2 (enExample) | 1988-04-14 |
Family
ID=14468243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10779678A Granted JPS5537229A (en) | 1978-09-01 | 1978-09-01 | Lapping method of wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5537229A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10210023A1 (de) * | 2002-03-07 | 2003-05-28 | Wacker Siltronic Halbleitermat | Siliciumscheibe und Verfahren zu ihrer Herstellung |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5344367Y2 (enExample) * | 1974-04-27 | 1978-10-24 | ||
| JPS5123896A (en) * | 1974-08-21 | 1976-02-26 | Hitachi Electronics | Usuitazaino shiagekakohoho |
-
1978
- 1978-09-01 JP JP10779678A patent/JPS5537229A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5537229A (en) | 1980-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5964646A (en) | Grinding process and apparatus for planarizing sawed wafers | |
| JPH0636414B2 (ja) | 半導体素子形成用基板の製造方法 | |
| US6352927B2 (en) | Semiconductor wafer and method for fabrication thereof | |
| KR20010030567A (ko) | 반도체 웨이퍼의 가공방법 | |
| US3951728A (en) | Method of treating semiconductor wafers | |
| JPS6317590B2 (enExample) | ||
| JPH08274285A (ja) | Soi基板及びその製造方法 | |
| JPH05226305A (ja) | 張合せウェハの製造方法 | |
| TW200403739A (en) | Method of machining silicon wafer | |
| JPH02208931A (ja) | 化合物半導体基板の研磨方法 | |
| JPS62132324A (ja) | ウエハ−の面取り研削ダメ−ジ層の除去方法および除去用治具 | |
| JPS61158145A (ja) | 半導体基板の加工方法 | |
| JP3821944B2 (ja) | ウェーハの枚葉式研磨方法とその装置 | |
| JPS6240141B2 (enExample) | ||
| US11534889B2 (en) | Polishing pad for wafer polishing apparatus and manufacturing method therefor | |
| JPH07201789A (ja) | 化合物半導体ウェハの両面ラッピング方法 | |
| JPH07302774A (ja) | 半導体基板の研磨方法、その装置、及び半導体基板の研磨用貼付プレート | |
| JPH05114593A (ja) | 半導体ウエハーの研削方法 | |
| JPS5972139A (ja) | 薄板材の加工方法 | |
| JPS59188921A (ja) | 誘電体分離基板の製造方法 | |
| JP2950497B2 (ja) | 半導体ウェ−ハおよびその製造方法 | |
| JPS62181869A (ja) | 半導体ウエハの研磨方法 | |
| JPH02294032A (ja) | ウエハー研磨方法及び研磨装置 | |
| JPH02178927A (ja) | 板面体の研磨方法 | |
| JPS58168243A (ja) | 半導体ウエ−ハの処理方法 |