JPS63167786U - - Google Patents
Info
- Publication number
- JPS63167786U JPS63167786U JP6040987U JP6040987U JPS63167786U JP S63167786 U JPS63167786 U JP S63167786U JP 6040987 U JP6040987 U JP 6040987U JP 6040987 U JP6040987 U JP 6040987U JP S63167786 U JPS63167786 U JP S63167786U
- Authority
- JP
- Japan
- Prior art keywords
- conductor pattern
- solder
- integrated circuit
- solder plating
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 4
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は本考案の一実施例を示す混成集積回路
の底面図、第２図は第１図のＡ―Ａ′線での断面
で混成集積回路を示したプリント板実装時の断面
図、第３図は従来のこの種の混成集積回路装置の
プリント板への搭載時の一例を示す断面図である
。
１……リードレスタイプの混成集積回路装置基
板、２……半田メツキを行なつた配線用導体パタ
ーン、３……半田メツキを行つた補助導体パター
ン（半田メツキを含む）、４……半田、５……プ
リント板。
FIG. 1 is a bottom view of a hybrid integrated circuit showing an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA' in FIG. 1, showing the hybrid integrated circuit when mounted on a printed board; FIG. 3 is a sectional view showing an example of a conventional hybrid integrated circuit device of this type when it is mounted on a printed board. 1... Leadless type hybrid integrated circuit device board, 2... Solder-plated wiring conductor pattern, 3... Solder-plated auxiliary conductor pattern (including solder plating), 4... Solder, 5... Printed board.
Claims (1)
メツキを行なつた混成集積回路において、前記回
路基板の前記底面の余白部分に補助導体パターン
を設け、該補助導体パターンに半田メツキを施し
て、前記配線用導体パターン上の半田メツキと前
記補助導体パターン上の半田メツキとを同じ高さ
としたことを特徴とする混成集積回路装置。 In a hybrid integrated circuit in which solder plating is performed on the wiring conductor pattern on the bottom surface of the circuit board, an auxiliary conductor pattern is provided in the margin part of the bottom surface of the circuit board, and the auxiliary conductor pattern is solder-plated. A hybrid integrated circuit device characterized in that the solder plating on the wiring conductor pattern and the solder plating on the auxiliary conductor pattern are the same height.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040987U JPS63167786U (en) | 1987-04-20 | 1987-04-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040987U JPS63167786U (en) | 1987-04-20 | 1987-04-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63167786U true JPS63167786U (en) | 1988-11-01 |
Family
ID=30892795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6040987U Pending JPS63167786U (en) | 1987-04-20 | 1987-04-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63167786U (en) |
-
1987
- 1987-04-20 JP JP6040987U patent/JPS63167786U/ja active Pending