JPS63155765A - Semiconductor device - Google Patents

Abstract

PURPOSE:To secure a direct contact between a gate electrode and a diffusion layer so as to obtain high integration therein, by using an insulating material including a group V element or a group III element so as to form a side wall of a gate electrode in a MOS transistor. CONSTITUTION:This device comprises the following parts: a P type semiconductor substrate 11, a gate electrode 12 made of polysilicon, an N<+> diffusion layer 13 formed just under the gate electrode, an N<+> type diffusion layer 14 which composes a drain region and a source region, a gate oxidizing film 15 made of SiO2, a contact window 16, a side wall 17 made of PSG, an N<+> type region 18 highly concentrated by mixture of phosphorus atoms from the side wall 17, and a field region 19 which is made of SiO2 so as to perform element isolation. A concentration of donors in the side wall 17 is increased since phosphorus atoms are mixed into a region just under the side wall. Therefore, a direct contact between a gate electrode 12 and the N<+> type diffusion layer 14 can be secured through the N<+> type diffusion layer 13 and the highly concentrated N<+> type region 18.

Description

[Detailed Description of the Invention] [Summary] A semiconductor device having an MIS transistor with a lightly doped drain structure, the sidewalls of the gate electrode of this transistor being made of an insulating material containing a Group V or Group II element. By forming the gate electrode, good direct contact between the gate electrode and the diffusion layer can be achieved.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a Mo5 (metal oxide semiconductor) transistor with a low concentration drain structure (hereinafter referred to as an LDD structure) and a wider (MIS (metal insulator semiconductor) transistor). .

[Prior art and problems to be solved by the invention]

SRAM (static random access memory)
In memory devices such as
For example, memory cells, word lines from the array (Mo3)
A technique is used in which the gate electrode (corresponding to the gate electrode of the Randisk) is connected to the word decoder, in which the gate electrode is brought into direct contact with the diffusion layer in the substrate. FIG. 3 shows a cross-sectional view of a normal MoS transistor in which the gate electrode and the diffusion layer are in direct contact. In the figure, 31 is a semiconductor substrate, 32 is a gate electrode, 33 is an N-type diffusion layer formed directly under the gate electrode, 34 is an N-type diffusion layer forming a drain or source region, and 35 is a D1-oxide film. , 36 indicate a contact window. As shown in the figure, the gate electrode 32 and the N-type diffusion layer 34 are in direct contact through the N-type resistive diffusion layer 33 directly below the gate electrode.

However, recently, techniques have been used to miniaturize gate electrodes in order to achieve even higher integration. In this case, the width of the gate electrode, that is, the gate length, is approximately 2
It does not affect the performance of the transistor if it is down to about 2 μm, but when it is miniaturized to about 2 μm or less, the electric field strength increases relatively, especially at the drain end, which causes the disadvantage that the breakdown voltage decreases. arise.

In order to cope with this problem, an LDI (LDI) structure transistor was devised, an example of which is shown in FIG. In the same figure, 31 to 36 indicate the same components as shown in FIG.
Shows a shaped wave scattering layer. In a transistor with an LDD structure, the impurity concentration is lowered at the train end (also the source end), thereby reducing the electric field strength and thereby preventing a drop in breakdown voltage.

However, as shown in FIG. 4, according to the LDD structure, since a low concentration (N→ diffusion IW 38) is interposed between the gate electrode 32 and the N-type diffusion layer 34, direct contact is ensured. The problem arises that it is difficult to take

The present invention was created in view of the problems in the prior art described above, and provides a semiconductor device that ensures direct contact between a gate electrode and a diffusion layer, thereby contributing to high integration. is intended to provide.

[Means and effects for solving the problem] A semiconductor device according to the present invention has a MOS l-transistor with an LDD structure, and the side wall of the gate electrode of the transistor contains an element of group V or group It is characterized by being formed of an insulating material containing.

For example, taking an N-channel type MOS transistor as an example, if an insulating material containing a Group V element, such as I) (phosphorus) is used as the sidewall, the phosphorus will be mixed into the region directly under the sidewall, and this will cause the Since the impurity concentration in the region increases, reliable direct contact is formed between the gate electrode and the diffusion layer.

〔Example〕

FIGS. 1(a), 1(b), and 1(c) show the structure of a semiconductor device as an embodiment of the present invention. In the figure, 1
1 is a P-type semiconductor substrate, 12 is a gate electrode made of polysilicon, 13 is an N+ type diffusion layer formed directly under the gate electrode, 14 is an N+ type diffusion layer constituting a drain region or a source region, and 15 is SiO□ A gate oxide film consisting of
16 is a contact window, 17 is a side wall formed of PSG (phosphosilicate glass), and 18 is an N-shaped region 19 which is highly concentrated due to the mixing of phosphorus atoms from the side wall 17 and is made of 5iO7.
A field region for isolation between elements consisting of is shown.

According to the apparatus of FIG. 1, PSG containing phosphorus as the side wall 17
is used, so that when formed as a sidewall, phosphorus atoms that can act as donors are mixed into the region directly under the sidewall, thereby increasing the donor concentration. Therefore,
As shown in the figure, the gate electrode 12 and the N+ type diffusion F'
14 can be reliably brought into direct contact via the N'' type diffusion layer 13 and the heavily doped N'' shadow region 18 directly under the gate electrode.

2(a) to 2(g) show the manufacturing process of the device shown in FIG. 1. The cross-sectional views at each step in Fig. 2 are shown in Fig. 1(a).
A sectional view taken along line A-A of FIG.

First, in step (a), a total of 15 SiO□ films 15 are formed as a gate insulating film on the substrate 11 in the active region.

In step (b), a resist is used to remove all 15 portions of the SiO□ film 15 corresponding to predetermined regions, that is, regions where direct contact between the gate electrode and the diffusion layer is desired. In the next step (C), a polysilicon gate electrode 12 is formed. As a result, a high concentration (N) diffusion layer 13 is formed directly under the gate electrode.

In step (cf), low temperature (N-) diffusion layers 20 are formed on both sides of the N'' type diffusion layer 13 directly under the gate electrode to form a l-D structure. In step (e), side walls 17 are formed. After depositing PSG on the entire surface of the structure in step (d), the side wall 17 is deposited by anisotropic RIE using, for example, CF (carbon tetrafluoride) gas.
It is formed by the reactive ion etching method. Process (
f) Using the edge of the side wall 17 of the tobacco, the N-swelling diffusion layer 2 is formed.
An N-type diffusion layer 14, that is, a diffusion layer constituting a drain region or a source region, is formed outside the region 0.

In the final step (g), virtually no treatment is performed, but since PSG is used as the material for the side wall 17, that is, an insulator containing phosphorus atoms that can act as donors, the step (f) After the treatment in ), a heat treatment causes phosphorus atoms in the sidewall 17 to mix into the N-swelling diffusion layer 20, thereby increasing the donor concentration in the diffusion layer. As a result, the N-swelling diffusion layer 20 changes to a region 18 of high temperature (N'). As a result, the gate electrode 12 becomes N
Direct contact is reliably made with the N+ type diffusion layer 14 via the + type diffusion layer 13 and the N+ type region I8.

Note that although an N-channel type was used in this embodiment, for example, a P-channel type was used.
Even when a channel type structure is used, a similar effect can be expected by forming the sidewalls with an insulating material containing a group Ⅰ element.

〔Effect of the invention〕

As explained above, according to the present invention, direct contact between the gate electrode and the diffusion layer can be established reliably, and thereby high integration can be achieved.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (c) are diagrams showing the structure of a semiconductor device as an embodiment of the present invention, and FIGS. 2(a) to (g) are manufacturing process diagrams of the device shown in FIG. , FIG. 3 is a cross-sectional view for explaining direct contact in a normal MOS transistor, and FIG. 4 is a cross-sectional view for explaining direct contact in an LDD structure MOS transistor. (Explanation of symbols) 11... Semiconductor substrate, 12... Gate electrode, 1
3.1-4...N+ type diffusion layer, 15...5in2 film, 16... Contact window, 17... Side wall (PSG)
, 18...N-shaped area 19... Field area.

Claims (1)

[Claims] 1. It has a MIS transistor with a low concentration type drain structure, and the side wall (1) of the gate electrode (12) of the MIS transistor
7) A semiconductor device in which the semiconductor device is formed of an insulating material containing a Group V or Group III element. 2. The semiconductor device according to claim 1, wherein the insulating material is phosphosilicate glass.