JPH05183131A - Thin film transistor - Google Patents

Abstract

PURPOSE:To improve source.drain withstand voltage of a thin film transistor. CONSTITUTION:An N-type channel region 5 is connected to a P-type high- concentration drain region 6 through a offset region 8. The offset region 8 is a polysilicon which is not doped with impurities substantially. Therefore, source.drain withstand voltage is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a polysilicon thin film transistor used as a load element of a static RAM.

[0002]

2. Description of the Related Art A thin film transistor having a channel formed of a polysilicon film deposited on a gate electrode via a gate insulating film is used.
r, hereinafter referred to as TFT) is used as a load element of the static RAM.

A conventional TFT will be described with reference to FIG. First, a silicon oxide film 2 having a thickness of 200 to 300 nm and a gate electrode 3 made of polycrystalline silicon having a thickness of 100 to 150 nm are formed on a silicon substrate 1 by a CVD method.

Next, the gate insulating film 4 having a thickness of 15 to 35 nm is formed by the CVD method. Next, a thickness of 20 to 50 nm provided by a CVD method to form a channel of the TFT
1 x 1 phosphorus by ion implantation into the polycrystalline silicon film of
The N-type channel region 5 is formed by introducing it so as to have an impurity concentration of 0 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ³ .
Next, with the photoresist film as a mask, 1 × 10 ¹⁹ boron was added to the polycrystalline silicon film in which the N-type channel region 5 was formed.
The impurities are introduced so as to have an impurity concentration of 1 × 10 ²⁰ atoms / cm ³ to form the high-concentration P-type drain region 6 and the high-concentration P-type source region 7.

Here, an offset structure is formed in which the high-concentration P-type drain region 6 is separated from the TFT channel region 5,
The fact that the on / off characteristics of the TFT can be improved by making the impurity concentration of the offset region P-type having a lower efficiency than that of the high-concentration P-type drain region 6 is described in, for example, Spring 38 of 1991.
Proceedings of the 12th Joint Lecture on Applied Physics No. Two
P. 671, 30p-T-2. That is, boron is added to the TFT of FIG. 3 in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ a.
By providing the low-concentration P-type impurity region 9 formed by introducing so as to have an impurity concentration of toms / cm ³ , the on / off characteristics are improved. Finally, an interlayer insulating film, a metal wiring, a surface protective film, etc. are formed to complete the TFT.

[0006]

In the conventional TFT, the offset region 9 has a low concentration P type in order to improve the on / off characteristics. 4-megabit class static RAM
Then, the gate long wave of the TFT used as a load is 1.0 to 1.
It is about 4 μm, but if the miniaturization of the device progresses, T
When the gate length of the FT is shortened, the breakdown voltage between the source and the drain is greatly reduced, and the characteristics of the TFT are deteriorated. In particular, when the offset region 9 is of a low concentration P type for a conventional TFT, the reduction in source-drain breakdown voltage due to miniaturization is remarkable.

[0007]

SUMMARY OF THE INVENTION The gist of the present invention is to form a gate electrode on a main surface of a semiconductor substrate and to face the gate electrode with a gate insulating film interposed between the gate electrode and the gate electrode. A first conductivity type channel region, a high concentration second conductivity type source region formed in the polycrystalline silicon film adjacent to the channel region, and a high concentration second conductivity type source region provided in the polycrystalline silicon. In a thin film transistor having a drain region and an offset region provided in the polycrystalline silicon film and interposed between the channel region and the drain region, the offset region is polycrystalline silicon in which substantially no impurities are introduced. That is.

[0008]

In the conventional TFT, the high-concentration P-type drain region is brought into contact with the low-concentration P-type offset region to relax the electric field near the drain and reduce the leak current when the TFT is off.

The TFT of the present invention is used in a state where no impurities are introduced into the portion of the polycrystalline silicon film which is in contact with the high-concentration second conductivity type drain region, whereby the width of the depletion layer at the drain end is widened and the drain electric field is increased. TFT by relaxing
It is possible to reduce the leak current at the time of off. In this case, by setting the width of the offset region larger than the maximum width of the depletion layer, it is possible to prevent the breakdown voltage between the source and drain from being lowered.

[0010]

The present invention will now be described with reference to the embodiments shown in the drawings. FIG. 1 is a vertical sectional view showing a first embodiment of the present invention. The TFT of the first embodiment functions as a load element of a flip-flop type static memory cell.

A silicon substrate 1 having a thickness of 20 is formed by a CVD method.
0 to 300 nm silicon oxide film 2 and thickness 100 to 1
A gate electrode 3 made of polycrystalline silicon having conductivity of 50 nm is formed.

Next, the thickness is 15 to 35 nm by the CVD method.
The gate insulating film 4 is formed. Next, a polycrystalline silicon film having a thickness of 20 to 50 nm is formed by a CVD method to form a channel of the TFT, and phosphorus is added by 1 × 10 ¹⁷ to 1 × by an ion implantation method using a photoresist film as a mask.
The N-type channel region 5 is formed by introducing it into only the region which becomes the channel of the TFT so that the impurity concentration becomes 10 ¹⁸ atoms / cm ³ .

Next, using the photoresist film as a mask, boron is introduced into the polycrystalline silicon film provided with the N-type channel region 5 so as to have an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ , and a high concentration is obtained. Concentration P-type drain region 6 and high concentration P-type source region 7 are formed. Here, the N-type channel region 5 of the TFT and the high-concentration P-type drain region 6 are separated by an offset region 8 in which no impurities are introduced. Finally, the TFT is completed by forming an interlayer insulating film, a metal wiring, a surface protective film, and the like.

Next, a second embodiment of the present invention will be described with reference to FIG. Similar to the first embodiment, 1 is a silicon substrate and 2 is a silicon oxide film. Here, a thickness of 20 to 50 n is formed by a CVD method to form a channel of the TFT.
m polycrystalline silicon film is provided, and phosphorus is introduced by the whole surface ion implantation method so as to have an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms / cm ^{3 and} a polycrystalline silicon film including the N-type channel region 5 is formed. To form.

Next, after forming the gate insulating film 4 having a thickness of 15 to 35 nm by the CVD method, the thickness of 100 to 150 n is obtained.
A gate electrode 3 made of polycrystalline silicon having a conductivity of m is formed.

Next, using the gate electrode 3 as a mask, boron is introduced by an ion implantation method so as to have a dose amount similar to that of phosphorus introduced into the N-type channel region 5. In this case, by adjusting the dose amount of boron to be introduced, the final impurity concentration of the offset region 8 can be made the same as that of the polycrystalline silicon film in which no impurity is introduced.

Next, using the photoresist film as a mask, boron is added to the N-type polycrystalline silicon film 5 at a concentration of 1 × 10 ¹⁹ to 1 × 10 ^20.
Introduced so as to have an impurity concentration of atoms / cm ³ ,
High-concentration P-type drain region 6 and high-concentration P-type source region 7
To form. Finally, the TFT is completed by forming an interlayer insulating film, a metal wiring, a surface protective film and the like as in the previous embodiment.

Although the above embodiments have described the case where the P-type TFT is formed, the same effect as that of the P-type TFT is provided by providing the offset region in which the impurity is not introduced even when the N-type TFT is formed. Can be obtained.

[0019]

As is apparent from the above description, the TFT of the present invention is substantially doped with impurities provided in the polycrystalline silicon film between the N-type channel region and the high-concentration P-type source region. Since there is no offset region, there is an effect that the on / off characteristics of the TFT can be improved without lowering the breakdown voltage between the source and drain.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view of a conventional example.

[Explanation of symbols]

 1 Silicon Substrate 2 Silicon Oxide Film 3 Gate Electrode 4 Gate Insulating Film 5 N-type Channel Region 6 High-concentration P-type Drain Region 7 High-concentration P-type Source Region 8 Offset Region 9 Low-concentration P-type Offset Region

Claims (3)

[Claims] 1. A gate electrode, a first conductivity type channel region formed on one main surface of a semiconductor substrate, the channel region being defined in a polycrystalline silicon film and opposed to the gate electrode via a gate insulating film. A high-concentration second-conductivity-type source region formed in the polycrystalline silicon film and adjacent to a channel region; a high-concentration second-conductivity-type drain region provided in the polycrystalline silicon film; A thin film transistor having an offset region provided between the channel region and the drain region, wherein the offset region is polycrystalline silicon into which substantially no impurities are introduced. 2. The thin film transistor according to claim 1, wherein the first conductivity type is N type, and the second conductivity type is P type. 3. The thin film transistor according to claim 1, wherein the thin film transistor functions as a load element of a flip-flop type static memory cell.