JPS63152093A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JPS63152093A
JPS63152093A JP61298896A JP29889686A JPS63152093A JP S63152093 A JPS63152093 A JP S63152093A JP 61298896 A JP61298896 A JP 61298896A JP 29889686 A JP29889686 A JP 29889686A JP S63152093 A JPS63152093 A JP S63152093A
Authority
JP
Japan
Prior art keywords
row
address
column
bit
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61298896A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0444355B2 (enrdf_load_stackoverflow
Inventor
Junji Ogawa
淳二 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61298896A priority Critical patent/JPS63152093A/ja
Priority to US07/132,442 priority patent/US4811297A/en
Priority to KR1019870014361A priority patent/KR910002202B1/ko
Priority to EP19870402882 priority patent/EP0272980A3/en
Publication of JPS63152093A publication Critical patent/JPS63152093A/ja
Publication of JPH0444355B2 publication Critical patent/JPH0444355B2/ja
Granted legal-status Critical Current

Links

JP61298896A 1986-12-16 1986-12-17 半導体記憶装置 Granted JPS63152093A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP61298896A JPS63152093A (ja) 1986-12-17 1986-12-17 半導体記憶装置
US07/132,442 US4811297A (en) 1986-12-16 1987-12-14 Boundary-free semiconductor memory device
KR1019870014361A KR910002202B1 (ko) 1986-12-16 1987-12-15 바운더리-프리 반도체 메모리 장치
EP19870402882 EP0272980A3 (en) 1986-12-16 1987-12-16 Boundary-free semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61298896A JPS63152093A (ja) 1986-12-17 1986-12-17 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPS63152093A true JPS63152093A (ja) 1988-06-24
JPH0444355B2 JPH0444355B2 (enrdf_load_stackoverflow) 1992-07-21

Family

ID=17865558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61298896A Granted JPS63152093A (ja) 1986-12-16 1986-12-17 半導体記憶装置

Country Status (1)

Country Link
JP (1) JPS63152093A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0444355B2 (enrdf_load_stackoverflow) 1992-07-21

Similar Documents

Publication Publication Date Title
US5436870A (en) Semiconductor memory device
US6011751A (en) Sychronous semiconductor memory device with burst address counter operating under linear/interleave mode of single data rate/double data rate scheme
KR910002202B1 (ko) 바운더리-프리 반도체 메모리 장치
KR20020033497A (ko) 반도체장치
EP0189576B1 (en) Multiple pixel mapped video memory system
US5535163A (en) Semiconductor memory device for inputting and outputting data in a unit of bits
JP3703518B2 (ja) 連想メモリシステム
JPH03216888A (ja) 半導体記憶装置
US4773045A (en) Semiconductor memory device with shift during write capability
CA1207916A (en) Cmos multiport general purpose register
US5396460A (en) FIFO memory in which number of bits subject to each data read/write operation is changeable
JPH065070A (ja) シリアルアクセスメモリ
JP3096362B2 (ja) シリアルアクセスメモリ
JPS63152093A (ja) 半導体記憶装置
US4962486A (en) Boundary-free semiconductor memory device having a plurality of slide access memories
JPS60142449A (ja) デ−タ変換回路
JPH0344888A (ja) 半導体記憶装置
JP3090104B2 (ja) 半導体メモリ装置
US6735147B2 (en) Semiconductor memory device and a method for generating a block selection signal of the same
US6442097B2 (en) Virtual channel DRAM
KR100546297B1 (ko) 반도체 집적회로
JPH0255877B2 (enrdf_load_stackoverflow)
JP2000076845A (ja) 記憶装置および記憶装置の制御方法
JP3359932B2 (ja) プログラマブル・ロジック・ユニット回路及びプログラマブル・ロジック回路
KR0150856B1 (ko) 반도체기억장치 및 그 데이터리드방법

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees