JPS63152093A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize reduction and expansion of a pit aggregate, by nullifying a part of cell at the time of rearranging the cell by an arranging means. CONSTITUTION:A memory cell is divided into n-rows of memory cell blocks B0-Bn-1, and n-number of serial transfer means SR0-SRn-1 are arranged in parallel in the row direction of each memory cell block, and n-number of same row selecting means DR are provided in the memory cell block of each row. A switching means RSW supplies a row address AR or a row address AR+1 adjacent to the row address. At the time of a serial access mode, a transfer means TR connects in series one row of each memory cell block to a corresponding serial transfer means comprehensively, and the arranging means BAC connects the serial transfer means to n-number of serial input/output terminals SIO0-SiOn-1 after rearrangement. In such a way, it is possible to access by the pit aggregate of arbitrary n-rows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a boundary-free semiconductor memory device used for multidimensional data processing such as image data processing.

[Conventional technology]

For example, in image processing, an image memory is used to store image data, and this image memory often stores image data corresponding to an image displayed on a graphic display or the like.

The conventional dual-port dynamic RAM for images is replaced with a second one.
This will be explained with reference to Figure 1. In Figure 20, 1M
The bit map configuration of the bit memory cell array MCA is shown. That is, 1024 memory cells are arranged along the X direction, and 1024 memory cells are arranged along the Y direction.

Furthermore, serial access memory SAMO-SAM3
are arranged along the row direction of memory cell array MCA. Here, each serial access memory SAMO~
SAM3 is composed of a 1024-bit shift register. Therefore, in the serial access mode, data for four rows of memory cell array MCA is simultaneously transferred in parallel to the serial access memories SAMO to SAM3, and the serial data so out 〜sou'
Transferred as r:+. On the other hand, in the random access mode, the 4-bit cell designated by the row addresses RAO-RA7 and column addresses CAO-CA9 is accessed and connected to the input/output terminals 0-101.

[Problem that the invention seeks to solve]

However, in the semiconductor memory device of FIG.
In the serial access mode, parallel transfers of the 1st to 4th lines, parallel transfers of the 5th to 8th lines, etc. are performed.
Even if addresses are logically scrambled, it is impossible to access four adjacent rows at any location from the logical bitmap plane. In other words, there are transfer boundaries for each solid line shown in FIG. To solve this problem, it is possible to perform multiple parallel transfers and access any four adjacent rows by masking part of the serial access memories SAMO to SAM3 for each transfer. In this case, the control becomes complicated, the access time is long, and the data obtained is not in the order of adjacent rows.

On the other hand, in the random access mode, the 4-bit cells shown with diagonal lines in FIG.
o ”I 4-bit access is possible by connecting to Ox, but this 4-bit aggregate is row (Y)
It has boundaries not only in the direction but also in the column (X) direction. In this case, it is possible to access any 4-bit aggregate by performing several accesses, but the control is still complicated, the access time is long, and the data is not in the order of adjacent data.

Accordingly, an object of the present invention is to provide a boundary-free semiconductor memory device that allows access to bit sets of arbitrary adjacent n rows in serial access mode.

Furthermore, another object of the present invention is to provide a boundary-free semiconductor memory device that allows access to any bit aggregate shape in random access mode.

[Means for solving problems]

The means for solving the above problems are shown in Figures 1A and 1B.
As shown in the figure.

In FIG. 1A, the memory cells are divided into n rows of memory cell blocks B0, B+, . . . +BI%-t, and n serial transfer means SRa, SR, . ..., SR, - are arranged in parallel. Further, n identical row selection means RD are provided in common for each row of memory cell blocks, and the switch means R
5W gives each row selection means the row address Am or the row address A*+1 adjacent to the row address. In the serial access mode, the transfer means TR connects one row of each memory cell block accessed by each row selection means in parallel to the corresponding serial transfer means, and the alignment means BAC connects each serial transfer means into n serial transfer means. Column input/output terminal sro. Realign and connect to ~510fi-+. This makes it possible to access any n rows of bit aggregates. Note that in FIG. 1A, the memory cells are divided into memory cell blocks of n rows and 1 column, but may be divided into memory cell blocks of n rows and m columns (n≧22m≧2).

In FIG. 1B, the memory cells are arranged in memory cell blocks B0°, B6++...*B (1+
m-1; Bn. lE3++1...r Bl+11-1
;...;BR-In. .

B11-1+1+ ...+ B11-1+ 11-
In the row direction of each memory cell block, there are n
xm serial transfer means SR,. ,5RO1+...HS
Rn −+ + 1m −+ are arranged in parallel. Furthermore, n identical row selection means RD are provided in common for each row of memory cell blocks, and m identical column selection means CD are provided for each column of memory cell blocks. The first switch means R3W assigns a row address Al to each row selection means.
l or the row address A1 next to the row address
1+1, and the second switch means C8W gives each column selection means the column address A or the column address AC+1 adjacent to the column address.

In the serial access mode, the transfer means TR
connects one row of each memory cell block accessed by each row selection means in parallel to the corresponding serial transfer means,
The first alignment means BACI realigns and connects each serial transfer means to n serial input/output terminals (SIO0 to SIO5101). In the random access mode, the second alignment means BAC2 realigns the nxm cells of each memory cell block accessed by each row selection means and each column selection means.

This makes it possible not only to access a desired n-row bit collection, but also to access a desired rectangular bit collection.

In addition, AI calculates the upper ((
Similarly, A is the decimal address vector notation made up of (1-1+gzm) bits, excluding the lower Itog and m bits of the total number of bits l of the externally input column address. ) is a decimal address vector representation made up of bits.

[For production]

According to the means shown in FIG. 1A, in the serial access mode, adjacent n rows, for example, four rows, at any position on the logical bitmap plane are accessed, and the data are accessed in the order of adjacent row data by the first alignment means.

Furthermore, according to the means of FIG. 1B, 2, in the serial access mode it is the same as the means of FIG. 1A, but in the random access mode, the alignment means is partially n'Xm by invalidating the cells of
' (n l≦n, m'≦m) bit aggregates can be accessed. In other words, it is possible to reduce or expand the bit collection.

〔Example〕

First, the outline of the boundary-free semiconductor memory device according to the present invention will be explained with reference to FIG. In Figure 2,
In serial access mode, any row Y0 can be selected as a transfer address using row addresses RAO to RA9.
(0≦Y0≦1023) and four adjacent rows (Yo,
Yo+1+Y(1+2.

Yll+3) as serial access memory SAMO~S
Transmit serial data S in parallel to AM3. U? 0
~S0UT2. At this time, serial data S. Ufl~Soua, regardless of the address, rows Yo, Yo +1, Y6 +2, Y
A sorting circuit (not shown) moves 1 so that the order of
make

Further, in the random access mode, selection of one row Y0 is performed by a 10-bit row address RAO-RA9, and selection of one column X0 is performed by a 10-bit column address CAO-CA9. Here, 4×
Assuming that the rectangular bit collection No. 4 is accessed at the same time, in this case, when the pointing bit PB is specified on the bitmap and accessed, the neighboring points (within the thick line frame) of the pointing focus PB will also be accessed, and random Connected to access input/output terminals IO, -ro+i. At this time, if any bit on the bitmap can become such a pointing bit PB, there is no boundary within the chip, that is, the chip is boundary free.

Furthermore, when the pointing bit PB approaches the chip limit, a chip boundary exists. Therefore, in order to eliminate such chip boundaries, the boundaries are made circular. For example, as shown in Figure 3A, when the boundary exceeds the chip's row boundary, the area with a small row address is accessed at the same time, and as shown in Figure 3B, when the boundary exceeds the chip's column boundary, Sometimes, areas with small column addresses are also accessed at the same time, and as shown in FIG. access at the same time. Thereby, a chip boundary-free semiconductor memory device can be obtained.

FIG. 4 is a circuit diagram showing an embodiment of a semiconductor memory device (chip) according to the present invention. In FIG. 4, I M
(1048576) bits of memory cells are arranged in 16 cell blocks B0°lBO++..., B1. It is divided into. In other words, each cell block B0°, Bo++...

B2''J is s+iK (65536) bits.

Here, the memory cell bit map (see FIG. 2) is allocated to blocks as shown in FIG.

4 cell blocks B oo + Bo + r Box
One row decoder RDO is provided in common for r Boz, and j cell blocks B1゜+ Bz r
One row decoder RDI for BI2+813
are provided in common, and the four cell blocks B2゜, Bz+
One row decoder RD2 for +Bt□, Bz3
are provided in common, and four cell blocks B3°.

One row decoder RD3 is provided in common for B3+r832+B'32. These row decoders RDO-RD3 have the same configuration. the other 4
Two cell blocks B0゜, Bzo, Bgo, B
For 3°, one column decoder CDO is commonly provided for four cell blocks B. l+B,+82
One column decoder CDI for 1+83+
are provided in common, and four cell blocks BO2, Bl□
+BZ□.

For B11, one column decoder CD2 is commonly provided, and four cell blocks B. 31Bl.

One column decoder CD3 is provided in common for B 12 + B 33. These column decoders CDO to CD3 also have the same configuration.

Top 8 of 10-bit row addresses RAO to RA9
Bits RA2-RA9 are incremented by +1 (in decimal notation) by incrementer INR, and as a result, two addresses, +0 address (through) and +1 address (increment), are supplied to low side switches R5WO-RSW3. And these low side switches RSWO
-R5W3 switches two addresses, ie, +0 address and +1 address, according to the lower two bits RAO and RAI of the 10-bit row address and supplies them to each row decoder RDO to RD3. On the other hand, the upper 8 bits CA2 of the 10-bit column address CAO-CA9
~CA9 is +1 (10
decimal display) is added, and as a result, +0 address (through)
and +1 address (increment) are supplied to column side switches C5WO to C5W3. And these column side switches cswo~C5W
3 is the lower 2 bits C of the 10-bit column address
Two addresses, ie, 10 address and +1 address, are switched according to AO and CAL and supplied to each column decoder CDO to CD3. However, in this case, each cell is configured so that two bit lines are accessed, as will be described later, so the column side switch C5
The 1-bit output from WO~C3W3 is sent not to the column decoder but to the selector S1111 + S10rS
26 rS20; ””; 53(1+S31
Sent to 1322*s3s.

16 selectors S0゜* S I (1+ S t.,
Si. ;...;S,. + S ffl l S! !
＋S! 3 is the block data bus BDB 1 , B
It is connected to the bus alignment circuit BAC2 via DB2. This bus alignment circuit BAC2 has upper addresses RAO,
Selector S0゜~S according to RAI, CAO, CAI
13 and random access input/output terminal 10°~■0,6
Control connections with

For serial access mode, each cell block Bz
Shift registers SR,, are arranged in parallel in the row direction of J (i=o~3.j-0~3), and their outputs 5ROij are connected to multiplexers MPXO~MPX3, and serial data of multiplexers MPXO~MPX3 are Bus S
The order of RD and ~5RDi is changed by the bus alignment circuit BACI1, and the serial access input/output terminals 5I
O0 to 5t (connected to
Yo (low address of pointing bit PH) is selected and transferred in parallel to a 1024-bit x 4-row shift register via a transfer gate. In addition,
The 1024-bit x 1-row shift register is a shift register SR arranged in parallel in 4 cell blocks. , 5Ril
, SR Direct, , Consists of 5R13. Then, in asynchronous mode of random access and serial access,
The 1024 bit by 4 row shift register performs addressless data reading at a high speed clock rate, for example about 20-30 MHz.

Since the block allocation of the bitmap is done as shown in Fig. 5, each cell block B ill + B il
The 256 adjacent sense amplifiers of lB it r B iff (shown in FIG. 6) have every fourth bit on the bitmap. For this reason, the multiplexer MPXO
.about.MPX3 undergoes 4-bit-1-bit parallel-to-serial conversion, and therefore is used as a shift register SR. ~SR or multiplexer MPXO~4 of serial clock SC of MPX3
It operates with shift clocks P+ and P2 having twice the period. And four serial data buses 5RDO~S
RD, are rearranged to form four serial input/output terminals sro. ~
SIO! connected to.

The control circuit C0NT also receives external control signals such as a chip enable signal CE, a parallel transfer signal TR for serial access mode, a read/write signal R/W, a serial clock 5CLK, etc., and various internal control signals such as a parallel transfer signal. Generates TR, shift clocks P+, Pz, serial clock SC, etc. For example, the internal shift clock SC is generated by bumping the external shift clock 5CLK, the shift clocks P+ and Pz are generated by dividing the internal shift clock SC by 4, and the chip enable signal The internal transfer signal TR is generated from the transfer signal bottom (■).

FIG. 6 is a detailed circuit diagram around cell block B i j in FIG. 4. In FIG. 6, folded pit lines are used. That is, as shown in the partial detail diagram of FIG. 7, memory cells are provided at every other intersection of a pair of bit lines connected to one side of each sense amplifier SA and each word line. Note that the sense amplifier SA in FIG. 7 includes a P-channel transistor cross-coupled between the line PSA and the bit lines BLO and B, and an N-channel transistor cross-coupled between the line NSA and the bit lines BLO and The channel consists of a transistor, and the line P
It operates when SA is brought to a high potential and line NSA is brought to a low potential. In addition, in FIG. 6, the row decoder RD
, are 256 word lines WL, . ,WL5,1,・
..., W.L., 23. The column decoder CD selects one word line from the column selection signal CD,
. ,CDi,,,.

CDi+ 127 allows two pairs of bit lines e.g. BLO
.

TTT; BL 1 and NTT are selected and the intra-block data bus D B , j, is selected. I D B ij+. g D
Connect to B ij+ l + D B iJ+ 1,
Furthermore, these two pairs of intra-block data buses D B
,,,. , D B ij+. r DB iJ+ I
+ D B ij+ Any one pair of 1 is switch S
block data bus BDBnj selected by ij
, BDBn,.

Switch S1j is two data bus latches LO.

It is composed of L1 and two selectors 5ELO and 5ELI, and each selector is composed of an inverter (2), an AND circuit G, , G, and an OR circuit G3, as shown in FIG. That is, depending on 1 bit C5Wj of the column address, either one of the data bus latches LO and LL is connected to the block data bus BDBn4. BD
Connect to Bnj.

According to the configuration of cell block Bij shown in FIG. 6, each column decoder CDj has a 128-bit configuration, so
Useful for the reduction side of column decoders, thus increasing capacity,
Although useful for high integration, such a cell block configuration is merely an example in the present invention. In other words, it may be an oven bit linear type. Alternatively, each column decoder CDj may be configured to directly select one pair of bit lines from 256 pairs of bit lines. In this case, all 8-bit addresses from each column-side switch C5WO-CSWI are supplied to the corresponding column decoder CDj, and switch Sij is deleted.

Each shift register SR,, has 256 registers RGO
- RG255, shift clock P l +P2
The output of the register RGO is output as the output SRO,j of the shift register 88.

Next, random access mode will be explained.

In FIG. 4, when randomly accessing the 4×4 bit collection shown in the thick line frame in FIG. (CA9, CA8,...
, CA O) = (0000000011) Also, as the bitmap X coordinate, (RA9 , RA8 ,..., RA O) = (
0000000001) is given from the outside. In other words, if the upper 16 bits (RA9 to RA2, CA9 to CA2) of the address given to each cell block Bij are the same, a 4x4 address boundary as shown by the thick line frame in Figure 5 exists on the logical plane. . At this time, in order to always access the 4 bits whose X coordinate (column) is larger than the pointing bit and the 4 bits whose X coordinate (row) is larger than the pointing bit, the upper +16 bits
You can do it manually depending on whether it is 0 (through) or +1 (increment). In this way, the address boundary indicated by the thick line frame in FIG. 5 disappears.

The above-mentioned distinction between 10 (through) and +1 (increment) must be made for each cell block Bij, but for cell blocks in each row, for example, Boa r
Bo+ + Bog + BO3 is the low decoder RDO
is common, and the cell block in each column is, for example, B. . .

Bn. +B2゜+B3゜ share the column decoder CDO, so eight low side switches R3WO~R
Only 5W3 and column side switches C5WO to C5W3 are required.

As shown in FIG. 9, each switch R5WO-RSW3 (
or C3WO to C3W3) is a decoder DECI that decodes the lower two bits RAO, RAI (or CAO, CAI) of the row (or column) address,
It consists of an 8-bit selector SEL that operates according to the output SWT of the decoder DECI. Here, decoder DE
CI has different decoding logic depending on each switch.
This circuit satisfies the logical formula shown in Table 1.

Star-Up-1 Switch 5WT RSWO (RAO) + (RAI)RSW 1
(RA 1 )RSW 2 (
RA O) ・ (RA 1 )1? SW 3
φ cswo (cAb)+ (CAL)C3
匈 1 (CA 1) CSW 2
(CA O) ・ (CA 1) CSW 3
φ Here, since the bit aggregate has the same width in both the row direction and the column direction, the logical formula for the low side switch and the logical formula for the column side switch match, but the bit aggregate is 2×
8.3×5, etc., if the width in the one direction and the width in the column direction are different.

The logical formulas in Table 1 are illustrated by FIG.

Here, FIG. 10 is a diagram showing the row address boundary, and the three thick lines in the horizontal direction are the row address boundaries based on the upper 8 bits RA9 to RA2 of the row address. Here, 4 blocks B 0jlB Ij + B
2j+Bffj has a difference in the lower two bits of the Y coordinate (low) of the bitmap plane. accessed 4
The form of a ×4 bit collection is 1, n, I[I,
There are four types of TV. In the case of form ■, each cell block B does not cross the row address boundary.
oi + B Ij + B z= + B : Ij
The same external addresses RA9 to RA'2 remain as they are (
through). In case of form ■, only the row address of cell block B6j is +1 (increment)
and in the case of form (■), cell block B. j+Blj
Each row address of cell block B Oj + Blj is incremented by +1.
r B2J each row address +1 (increment)
let If you organize this, it will look like Table 2.

Table 1 is a logical expression of Table 2 using the lower two bits RAI and RAO of the row address indicating the pointing bit position.

Note that the same applies to the column address side.

In this way, a boundary-free 4x4 bit collection can be accessed from the bitmap, for example, data can be read out, but if data is continuously output to the random access input/output terminals IO, ~IO,, the image data will be This is inconvenient for neighborhood processing. For example, the 4×4 bit set corresponding to blocks shown in FIG. 11(A) is
If read without alignment, the result will be as shown in FIG. 11(B), where the pointing bit on the bitmap and other neighboring bits do not maintain the logical relationship of the 4×4 shape. Surface access differs depending on location. Actually, a random access input/output terminal arrangement as shown in FIG. 11(C) is desired.

In other words, 1) Pointing bit PB is always input/output terminal IO0
is accessed.

2) The 4 bits located at positions sequentially incremented in the X direction from pointing bit PB are IOo.

It is accessed in the order of IO+, IOx, and L O:l.

3) Then it is incremented in the Y direction and 2
), 4 at an incremented position in the X direction
Bit is 104, TO5, IO6.

It is accessed in the order of IOl.

Regardless of the address of the pointing bit PB, it is always 4x with ■0 correspondence shown in Figure 11 (C) from the top of the bit map.
A bus alignment circuit BAC2 is provided for accessing the 4 bit aggregates. The bus alignment circuit BAC2 is
As shown in FIG. 12, cell block B
The block data bus BDBij connected to ij is 16
The demultiplexer circuit DMPX (actually, 16 demultiplexers) operates to be connected to one of the random access input/output terminals I00 to IO,5, and each demultiplexer in the demultiplexer circuit DMPX. It has a decoder DEC2 to control. In this case, the decoder DEC2 controls the demultiplexer circuit DMPX according to the lower four pins RAI, RAO, CAI, and CAO of the row and column addresses. Note that the AND circuit in the demultiplexer circuit DMPX is composed of, for example, a CMOS switch shown in FIG. 13. The bus alignment circuit BAC2 configured in this manner has the correspondence shown in Table 3.
Connect bus block Bij and random access input/output terminal IOk.

However, the numbers in Table 3 indicate the IO numbers.

For example, "14" is 10. , is shown.

In the above embodiment, the pointing pit PB is located at the upper left corner of the 4×4 bit collection, but the position of the pointing pit PB can be changed. In this case, the internal address calculation section (
In other words, incrementer IN+? , INC) and change the bus alignment circuit 8AC2. Furthermore, if part of the bus alignment circuit BAC2 is made high impedance,
Boundary-free random access in a 4×4 surface shape can be changed to boundary-free random access in a 3×3 surface shape. In other words, boundary-free random access to multiple types of surface shapes is easily possible with the same chip.

Next, the serial access mode will be explained.

Figures 14A and 14B are the shift register RG of Figure 6.
, is a detailed circuit diagram of . In FIG. 14A, shift register RG is composed of 2-bit shift registers RGA and RGB constructed from CMOS circuits. Each shift register RGA (RGB) is connected to CMO5) transmission gate G1. 'C2CGz, G4),
and CMOS inverters I, , I2Cr3, I4.
). Each shift register RGA.

RGB is transferred by shift clock P1 (high level) and latched by shift clock Pz (high level). In addition, in FIG. 14B, the shift register RG1 is a 2-channel shift register composed of an NMOS dynamic circuit.
It consists of shift registers RGA'RGB' for bits. Each shift register RGA'(RGB') consists of transistors Q1 to Q:l (Q, to Q6) and capacitors C and (CZ). Each shift register RGA',
RGB' is transferred by the high level (or low level) of shift clock P and the high level (or low level) of shift clock P2, but in this case, the transfer mode is different from the potential of each node Nl, Nz. It depends on the potential of shift clocks P+ and Pz.

For example, if the operation of the shift register in FIG. 14A is
To explain with reference to the timing diagram shown in FIG. 15, the control circuit C0NT shown in FIG. 4 has a cycle four times that of the shift clock SC shown in FIG. 15(C).

Shift clocks Pr and Pt of (B) are generated.

Therefore, when the serial access mode is entered after batch parallel transfer (TR="l"), the transmission gates G, , G3 are opened by the high level of the shift clock P, and the potentials of each node N, , NZ are adjacent to each other. The transmission gates C2, G are opened by the next high level of the shift clock P2, and the inverter It.

12;1. ,! The latch circuit of , is launched.

In this way, the -period I2 of the shift clock p, (pz)
It is shifted by 1 bit at each time. In addition, the shift clock P,,P! is the shift clock SC (for example, period 30
~40n3), but these high levels are generated so as not to overlap with each other.

FIG. 16 shows data in cell block B i j being transferred to shift register R in serial access mode.

FIG. 3 is a timing diagram showing batch parallel transfer to. Note that during batch parallel transfer, serial transfer in shift registers SR, . is stopped. That is, shift clock P1 is held at low level and shift clock P2 is held at high level. For example, at time 1°, four word lines are selected by the operation of the RAS system as shown in FIG. 16(B), and then each sense amplifier operates. As a result, at time t2, as shown in FIG. 16(A), the potential difference between each bit line pair BL, BL becomes large. Then, at time t3, as shown in FIG. 16(C), each bit line potential is changed to each shift register RGi of shift register SR, (FIG. 14A,
Node N1 (see No. 14B).

It is transferred all at once to N2. As a result, the bit line potential is launched at nodes N, , N, as shown in FIG. 16(D). At this time, the output OUT of the first shift register RGO of each shift register SR, J changes as shown in FIG. 16(E).

In this way, after batch transfer, each shift register S
R and J perform serial transfer as serial access mode.

As mentioned above, the serial output SRO□, transferred from each shift register SR, , is connected to four multiplexers M
Parallel-serial conversion from 4 bits to 1 bit is performed by PXO to MPX3. Each multiplexer MPX, as shown in FIG. 17, is composed of four shift registers SRX, -SRX, and these shift registers are operated by a shift clock SC.

The serial data buses SRD, ~SRD, of the four multiplexers MPXO-MPX3 are connected to the bus alignment circuit B.
Connected to MCI.

The bus alignment circuit BMCI is configured as shown in FIG. 18, and the Y coordinate order Y(1
, YO+1, YO+2. YO+3 is made to correspond to serial input/output terminals 5106 to 5IOff. In this case, there are four ways, and one is selected by the decoder DfIC3 using row addresses RAO* and RA1'k. Note that the row addresses RAO* and RA1* are the row addresses RAO and RAI launched in registers (not shown) during parallel transfer.

The AND circuits shown in FIG. 18 are, for example, those shown in FIG. 13.

In this way, 4 rows (Yo) on the bitmap.

YO+1, yO+2, Yco+3) are four-row shift registers (SAMO, SAMI, SAM2, 54
M3), and in this case, it is necessary to transfer Yo,
Yo+1, Y6+2. Although not in the order of Yo+3, when serially transferred to serial input/output terminals 5IO0 to 5IO3, Y, , Y, +1, Y0+2
, Y, +3.

Further, as shown in FIG. 19, a bitmap as a modified example of FIG. 2 is converted into a space (X).

The present invention can also be extended to three dimensions (Y, Z) using a similar hierarchical method.

Furthermore, in image processing, the image data stored in the image memory is processed by (1) compressing, (2) taking a difference between the data stored at the adjacent address of the center focus, and (
3) Data processing such as smoothing, etc. For example, image dust removal processing may be performed to generate new data for the central bit.

For example, if the 3x3 data shown in Fig. 20 is output one after another,
Center bit a0, a a ←(2ao + (at +az+a3+a*
+aS+a, +ay+as)). Even in such a case, there is an advantage that the processing speed can be further increased by serially outputting and processing adjacent rows using the serial access mode. By the way, in the dual port dynamic RAM according to the present invention, the random access cycle is about 200 to 30.
0ns, serial access cycle is approximately 30-50n
a, the above-mentioned advantages are obvious.

Note that in the above description of the serial access mode, the case of data reading was explained, but the present invention can also be applied to the serial access mode of data writing.

〔Effect of the invention〕

As described above, according to the present invention, in the serial access mode, n adjacent rows are accessed in that order, and there is no transfer boundary.

Additionally, random access to bit aggregates of arbitrary size can be performed in that order and boundary-free.

[Brief explanation of the drawing]

1A and 1B are basic configuration diagrams of the present invention, FIG. 2 is a diagram showing a bitmap configuration, FIGS. 3A to 3C are diagrams explaining boundary free, and FIG. 4 is a semiconductor memory according to the present invention. FIG. 5 is a block circuit diagram showing an embodiment of the device; FIG. 5 is a diagram showing the block allocation of a bitmap according to the present invention; FIG. 6 is a detailed circuit diagram of the cell block in FIG. 4; FIG. Figure 8 is a detailed circuit diagram of the selector in Figure 6, Figure 9 is a detailed circuit diagram of the low side switch (column side switch) in Figure 4, Figure 10 is a detailed circuit diagram of the row address boundary. 11 is a diagram showing the cell block data of FIG. 4, FIG. 12 is a detailed circuit diagram of the bus alignment circuit of FIG. 4, FIG. 13 is a partial circuit diagram of FIG. 12, and 14A Figure 14B is a circuit diagram showing an example of the shift register in Figure 6, Figure 15 is a timing diagram showing the circuit operation in Figure 14A, and Figure 16 is a timing diagram showing the batch parallel transfer operation in Figure 6. , Fig. 17 is a detailed circuit diagram of the multiplexer shown in Fig. 4, Fig. 18 is a detailed circuit diagram of the bus alignment circuit shown in Fig. 4, Fig. 19 is a diagram showing a modification of Fig. 2, Fig. 20 21 is a diagram explaining image processing, and FIG. 21 is a diagram showing a conventional bitmap configuration. Bo. 1E3o++...: Cell block, RDO~R
D3: Low decoder, CDO~CD3: Column decoder, RSW O~RSW3: Low side switch, C3W O~
C3W3: Column side switch, BACI, BAC2
: Bus alignment circuit, S Ro. ~5R44: Shift register, MPX 0~MPX3: Multiplexer.

Claims (1)

[Claims] 1, n row memory cell block (B_0, B_1,...
・, B_n_-_1), and n serial transfer means (SR_0, SR_1, ..., SR_n_) arranged in parallel in the row direction of each memory cell block.
-_1), n identical row selection means (RD) commonly provided in the memory cell blocks of each row, and a row address (A_R) or a row address adjacent to the row address (A_R) for each row selection means; A_R+1); a transfer means (TR) for collectively connecting one row of each of the memory cell blocks accessed by each of the row selection means to the corresponding serial transfer means; The means is connected to n series input/output terminals (SIO_
What is claimed is: 1. A semiconductor memory device comprising: an alignment means (BAC) for realigning and connecting to SIO_n_-_1), and enabling access to a desired n-row bit collection. 2. Memory cell block of n rows x m columns (B_0_0, B
_0_1,...,B_0_,_n_-_1;B_1_
0, B_1_1,..., B_1_,_m_-_1;・
...;B_n_-_1_, _0, B_n_-_1_, _
1, ..., B_n_-_1_, _m_-_1), and n×m serial transfer means (SR_0_0, SR_0_1, . . . ) arranged in parallel in the row direction of each memory cell block.
SR_n_-_1_, __m_-_1), n identical row selection means (RD) provided in common to the memory cell blocks in each row, and m identical row selection means (RD) provided in common in the memory cell blocks in each column. identical column selection means (CD); first switch means (RSW) for supplying a row address (A_R) or a row address (A_R+1) adjacent to the row address to each of the row selection means; and each of the column selection means. a second column address that gives the column address (A_C) or the column address (A_C+1) next to the column address.
a switch means (CSW) for each of the above-mentioned row selection means; a transfer means (TR) for collectively connecting one row of each of the memory cell blocks accessed by each of the row selection means to the corresponding serial transfer means; series input/output terminals (SIO_
a first aligning means (BAC1) that realigns and connects to SIO_n_-_1); and n×m cells of each memory cell block accessed by each row selection means and each column selection means. a second alignment means (BAC2) for realigning the bits, and which makes it possible to access a desired n-row bit collection and also make it possible to access a desired rectangular bit collection. Device.