JPS63131457U - - Google Patents
Info
- Publication number
- JPS63131457U JPS63131457U JP2340487U JP2340487U JPS63131457U JP S63131457 U JPS63131457 U JP S63131457U JP 2340487 U JP2340487 U JP 2340487U JP 2340487 U JP2340487 U JP 2340487U JP S63131457 U JPS63131457 U JP S63131457U
- Authority
- JP
- Japan
- Prior art keywords
- diodes
- emitter
- anode
- cathode
- bias value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Picture Signal Circuits (AREA)
Description
第1図は本考案に係る雑音除去回路の実施例を
示す回路図、第2図はノイズ低減量の大きい場合
の入出力特性を示すグラフ、第3図はノイズ低減
量の小さい場合の入出力特性を示すグラフ、第4
図は従来の雑音除去回路の一例を示す回路図であ
る。
2…ノイズ、4…可変抵抗、5…トランジスタ
、9,10…ダイオード、14…トランジスタ。
Fig. 1 is a circuit diagram showing an embodiment of the noise removal circuit according to the present invention, Fig. 2 is a graph showing the input/output characteristics when the amount of noise reduction is large, and Fig. 3 is the input/output when the amount of noise reduction is small. Graph showing characteristics, 4th
The figure is a circuit diagram showing an example of a conventional noise removal circuit. 2... Noise, 4... Variable resistor, 5... Transistor, 9, 10... Diode, 14... Transistor.
Claims (1)
入力用エミツタホロワのエミツタに互いに逆並列
接続されたダイオードが接続され、これらダイオ
ードの出力側及びカソードを入力側とする一方の
ダイオードの該カソード側に所定レベルのバイア
ス値が設定され、アノードを入力側とする他方の
ダイオードの該アノード側は、任意のレベルのバ
イアス値に調整可能なバイアス調整用エミツタホ
ロワのエミツタに接続されたことを特徴とする雑
音除去回路。 Diodes connected in antiparallel to each other are connected to the emitter of the signal input emitter follower, into which a signal containing a noise component is inputted as a base, and a predetermined diode is connected to the output side of these diodes and the cathode side of one of the diodes whose cathode is the input side. A level bias value is set, and the anode side of the other diode whose input side is an anode is connected to the emitter of a bias adjustment emitter follower that can be adjusted to an arbitrary level bias value. circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987023404U JPH073733Y2 (en) | 1987-02-18 | 1987-02-18 | Noise elimination circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987023404U JPH073733Y2 (en) | 1987-02-18 | 1987-02-18 | Noise elimination circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63131457U true JPS63131457U (en) | 1988-08-29 |
JPH073733Y2 JPH073733Y2 (en) | 1995-01-30 |
Family
ID=30821683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987023404U Expired - Lifetime JPH073733Y2 (en) | 1987-02-18 | 1987-02-18 | Noise elimination circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH073733Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59133781A (en) * | 1983-01-19 | 1984-08-01 | Mitsubishi Electric Corp | Video signal processing circuit |
-
1987
- 1987-02-18 JP JP1987023404U patent/JPH073733Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59133781A (en) * | 1983-01-19 | 1984-08-01 | Mitsubishi Electric Corp | Video signal processing circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH073733Y2 (en) | 1995-01-30 |
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