JPS6448924U - - Google Patents
Info
- Publication number
- JPS6448924U JPS6448924U JP1987143434U JP14343487U JPS6448924U JP S6448924 U JPS6448924 U JP S6448924U JP 1987143434 U JP1987143434 U JP 1987143434U JP 14343487 U JP14343487 U JP 14343487U JP S6448924 U JPS6448924 U JP S6448924U
- Authority
- JP
- Japan
- Prior art keywords
- limiter
- base
- output
- output terminal
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第1図は、本考案のリミツタ回路を示す回路図
、第2図及び第4図は同回路の説明波形図、第3
図は従来のリミツタ回路、第5図は第3図の説明
波形図を示す。
1……クリツプ用のダイオード、2……クリツ
プ用のトランジスタ、3……直列抵抗、4……積
分用のコンデンサ、5……入力端子、6……出力
端子。
Figure 1 is a circuit diagram showing the limiter circuit of the present invention, Figures 2 and 4 are explanatory waveform diagrams of the circuit, and Figure 3 is a circuit diagram showing the limiter circuit of the present invention.
The figure shows a conventional limiter circuit, and FIG. 5 shows an explanatory waveform diagram of FIG. 3. 1... Diode for clipping, 2... Transistor for clipping, 3... Series resistor, 4... Capacitor for integration, 5... Input terminal, 6... Output terminal.
Claims (1)
出力端子間に接続した直列抵抗と、該直列入力抵
抗の両端に接続されたダイオード及びエミツタ・
ベース路が接続されたリミツタ用トランジスタと
、該リミツタ用トランジスタのベース・コレクタ
路に接続されたコンデンサより成り、前記出力端
子よりリミツタ出力を得ることを特徴としたリミ
ツタ回路。 An input terminal to which a signal is applied, a series resistor connected between the input terminal and the output terminal, and a diode and emitter connected across the series input resistor.
1. A limiter circuit comprising a limiter transistor having a base connected thereto, and a capacitor connected to the base-collector path of the limiter transistor, the limiter output being obtained from the output terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987143434U JPH0528814Y2 (en) | 1987-09-18 | 1987-09-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987143434U JPH0528814Y2 (en) | 1987-09-18 | 1987-09-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6448924U true JPS6448924U (en) | 1989-03-27 |
JPH0528814Y2 JPH0528814Y2 (en) | 1993-07-23 |
Family
ID=31410257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987143434U Expired - Lifetime JPH0528814Y2 (en) | 1987-09-18 | 1987-09-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0528814Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368150A (en) * | 1976-11-30 | 1978-06-17 | Nec Corp | Limiter circuit |
-
1987
- 1987-09-18 JP JP1987143434U patent/JPH0528814Y2/ja not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368150A (en) * | 1976-11-30 | 1978-06-17 | Nec Corp | Limiter circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0528814Y2 (en) | 1993-07-23 |
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