JPS5917618U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5917618U
JPS5917618U JP11236582U JP11236582U JPS5917618U JP S5917618 U JPS5917618 U JP S5917618U JP 11236582 U JP11236582 U JP 11236582U JP 11236582 U JP11236582 U JP 11236582U JP S5917618 U JPS5917618 U JP S5917618U
Authority
JP
Japan
Prior art keywords
switching element
amplifier
output
circuit
muting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11236582U
Other languages
Japanese (ja)
Inventor
長下　恒良
俊之 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp filed Critical Pioneer Corp
Priority to JP11236582U priority Critical patent/JPS5917618U/en
Publication of JPS5917618U publication Critical patent/JPS5917618U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は増幅器の一例を示す回路図、第３図は
この考案によるミューティジグ回路の一実施例を示す回
路図である。 １・・・増幅器、Ｑ、、　Ｑ、・・・トランジスタ、Ｃ
工〜Ｃ５・・・コンデンサ、Ｒ工〜Ｒ□２・・・抵抗。1 and 2 are circuit diagrams showing an example of an amplifier, and FIG. 3 is a circuit diagram showing an embodiment of a muting circuit according to this invention. 1...Amplifier, Q,, Q,...Transistor, C
Engineering~C5...Capacitor, R Engineering~R□2...Resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 増幅器の電源回路に設けられた第１スイツチング素子と
、このスイッチング素子の入力側とアース間に接続され
て電源出力を積分するとともにその積分出力を前記増幅
器に入力バイアスとして供給する積分回路と、この積分
回路の出力が設定レベルに上昇した時にオンとなって前
記第１スイツ＼チング素子をオン制御して電源を前記増
幅器に供給するための制御を行なう第２スイツチング素
子とによって構成されることを特徴とするミューティン
グ回路。a first switching element provided in the power supply circuit of the amplifier; an integrating circuit connected between the input side of the switching element and ground to integrate the power supply output and supply the integrated output to the amplifier as an input bias; and a second switching element that turns on when the output of the integrating circuit rises to a set level and controls the first switching element to be turned on to supply power to the amplifier. Features a muting circuit.
JP11236582U 1982-07-23 1982-07-23 Muting circuit Pending JPS5917618U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11236582U JPS5917618U (en) 1982-07-23 1982-07-23 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11236582U JPS5917618U (en) 1982-07-23 1982-07-23 Muting circuit

Publications (1)

Publication Number Publication Date
JPS5917618U true JPS5917618U (en) 1984-02-02

Family

ID=30260509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11236582U Pending JPS5917618U (en) 1982-07-23 1982-07-23 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5917618U (en)

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