JPS6421572U - - Google Patents
Info
- Publication number
- JPS6421572U JPS6421572U JP11511787U JP11511787U JPS6421572U JP S6421572 U JPS6421572 U JP S6421572U JP 11511787 U JP11511787 U JP 11511787U JP 11511787 U JP11511787 U JP 11511787U JP S6421572 U JPS6421572 U JP S6421572U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- voltage
- voltage source
- amplification stage
- small signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図はこの考案に係る映像増幅回路の一実施
例を示す回路図、第２図は第１図を負荷とする電
源供給系統を示す回路図、第３図は従来の映像増
幅回路の一例を示す回路図、第４図は第３図を負
荷とする電源供給系統を示す回路図である。
５１……小信号増幅段、５２……定電圧ダイオ
ード、６１……トランジスタ、６２……トランジ
スタ、６９……電圧源端子、７０……電圧源端子
、７１……出力増幅段。
Fig. 1 is a circuit diagram showing an embodiment of the video amplification circuit according to this invention, Fig. 2 is a circuit diagram showing a power supply system with the load shown in Fig. 1, and Fig. 3 is an example of a conventional video amplification circuit. FIG. 4 is a circuit diagram showing a power supply system using FIG. 3 as a load. 51... Small signal amplification stage, 52... Constant voltage diode, 61... Transistor, 62... Transistor, 69... Voltage source terminal, 70... Voltage source terminal, 71... Output amplification stage.
Claims (1)
電圧源と、 前記小信号増幅段からの信号を前記第１の電圧
源の供給する電圧分アツプシフトして導くレベル
シフト回路と、 このレベルシフト回路からの信号をベースに入
力する第１のトランジスタを含むと共に、この第
１のトランジスタにコレクタ・エミツタ路が直列
接続された第２のトランジスタを含む出力増幅段
と、 前記第１の電圧源の供給する電圧より高い電圧
を前記第２のトランジスタのコレクタに負荷抵抗
を介して供給する第２の電圧源と、 を具備したことを特徴とする映像増幅回路。[Claims for Utility Model Registration] A small signal amplification stage for small signal amplifying a video signal; a first voltage source supplying a power supply voltage to the small signal amplification stage; The circuit includes a level shift circuit that upshifts and leads by the voltage supplied by one voltage source, and a first transistor that inputs a signal from this level shift circuit to its base, and a collector-emitter path is connected in series with this first transistor. an output amplification stage including a second transistor connected; a second voltage source supplying a voltage higher than the voltage supplied by the first voltage source to the collector of the second transistor via a load resistor; A video amplification circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11511787U JPS6421572U (en) | 1987-07-29 | 1987-07-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11511787U JPS6421572U (en) | 1987-07-29 | 1987-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6421572U true JPS6421572U (en) | 1989-02-02 |
Family
ID=31356480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11511787U Pending JPS6421572U (en) | 1987-07-29 | 1987-07-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6421572U (en) |
-
1987
- 1987-07-29 JP JP11511787U patent/JPS6421572U/ja active Pending
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