JPH01133874U - - Google Patents
Info
- Publication number
- JPH01133874U JPH01133874U JP3082888U JP3082888U JPH01133874U JP H01133874 U JPH01133874 U JP H01133874U JP 3082888 U JP3082888 U JP 3082888U JP 3082888 U JP3082888 U JP 3082888U JP H01133874 U JPH01133874 U JP H01133874U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- video signal
- generating means
- constant voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案に係るコントラスト制御回路の
一実施例を示す回路図、第２図乃至第４図は本考
案の他の実施例を示す回路図、第５図及び第６図
は従来のコントラスト制御回路を示す回路図であ
る。
２４……ビデオ信号入力端子、２５……ビデオ
信号増幅用トランジスタ、３１……出力端子、３
３……制御回路、３５……コントラストボリユー
ム、３６……ツエナーダイオード、４４……周波
数補正用コンデンサ。
FIG. 1 is a circuit diagram showing one embodiment of a contrast control circuit according to the present invention, FIGS. 2 to 4 are circuit diagrams showing other embodiments of the present invention, and FIGS. 5 and 6 are circuit diagrams showing a conventional contrast control circuit. FIG. 3 is a circuit diagram showing a contrast control circuit. 24...Video signal input terminal, 25...Video signal amplification transistor, 31...Output terminal, 3
3... Control circuit, 35... Contrast volume, 36... Zener diode, 44... Frequency correction capacitor.
Claims (1)
し、エミツタが抵抗を介して基準電位点に接続し
、ベースから入力したビデオ信号を所定の増幅量
で増幅してコレクタから出力するビデオ信号増幅
用のトランジスタと、 このトランジスタのエミツタに現れるビデオ信
号のペデスタルレベルと同レベルの電圧を発生す
る定電圧発生手段と、 この定電圧発生手段と前記トランジスタのエミ
ツタとの間に接続されこのトランジスタの前記所
定の増幅量を変化させるコントラストボリユーム
とを具備したことを特徴とするコントラスト制御
回路。 (2) コレクタが抵抗を介して直流電圧源に接続
し、エミツタが抵抗を介して基準電位点に接続し
、ベースから入力したビデオ信号を所定の増幅量
で増幅してコレクタから出力するビデオ信号増幅
用のトランジスタと、 このトランジスタのエミツタに現れるビデオ信
号のペデスタルレベルと同レベルの電圧を発生す
る定電圧発生手段と、 この定電圧発生手段と前記トランジスタのエミ
ツタとの間に接続されこのトランジスタの前記所
定の増幅量を変化させるコントラストボリユーム
と、 このコントラストボリユームと並列に接続され
る周波数特性の補正用のコンデンサとを具備した
ことを特徴とするコントラスト制御回路。[Claims for Utility Model Registration] (1) The collector is connected to a DC voltage source via a resistor, the emitter is connected to a reference potential point via a resistor, and the video signal input from the base is amplified by a predetermined amplification amount. a transistor for amplifying a video signal and outputting it from the collector; a constant voltage generating means for generating a voltage at the same level as the pedestal level of the video signal appearing at the emitter of the transistor; and a constant voltage generating means and the emitter of the transistor. 1. A contrast control circuit comprising: a contrast volume connected between the transistors and changing the predetermined amplification amount of the transistor. (2) A video signal in which the collector is connected to a DC voltage source via a resistor, the emitter is connected to a reference potential point via a resistor, and the video signal input from the base is amplified by a predetermined amplification amount and output from the collector. an amplifying transistor; a constant voltage generating means for generating a voltage at the same level as the pedestal level of the video signal appearing at the emitter of the transistor; and a constant voltage generating means connected between the constant voltage generating means and the emitter of the transistor. A contrast control circuit comprising: a contrast volume for changing the predetermined amplification amount; and a frequency characteristic correction capacitor connected in parallel with the contrast volume.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3082888U JPH01133874U (en) | 1988-03-07 | 1988-03-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3082888U JPH01133874U (en) | 1988-03-07 | 1988-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133874U true JPH01133874U (en) | 1989-09-12 |
Family
ID=31256229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3082888U Pending JPH01133874U (en) | 1988-03-07 | 1988-03-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133874U (en) |
-
1988
- 1988-03-07 JP JP3082888U patent/JPH01133874U/ja active Pending
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