JPS63122154A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the wiring capacitance effectively by a method wherein one out of a wiring part at a first layer and the wiring part at a second layer, the wiring part at the second layer and the wiring part at a third layer, or the wiring part at the first layer and the wiring part at the third layer is extended in the identical direction so as to be overlapped and an inphase signal is transmitted. CONSTITUTION:The output sides of inverter circuits IN1, IN2 whose input sides are connected to a clock source S are connected to wiring parts 5a and 9a. The other ends of the wiring parts 5a and 9a are connected to gates G1, G2 which are composed of a bipolar transistor or a MISFET. At this structure, inphase clock pulses P1, P2, which rise and fall at the same time and whose pulse width is the same, are transmitted to the wiring parts 5a and 9a. Through this constitution, the potential difference between the wiring parts 5a and 9a is always zero (0). In addition, the stray capacitance generated between the wiring part 5a and a wiring part 11 at the top layer can be made effectively zero because the wiring part 5a is shielded by the wiring part 9a. On the other hand, at the wiring part 9a the capacitance generated between this wiring part and a semiconductor substrate 1 is shielded by the wiring part 5a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to wiring of a semiconductor integrated circuit device.

[Conventional technology]

Wiring in semiconductor integrated circuit devices tends to be multilayered as the degree of integration increases. Technology related to multilayer wiring and wiring pattern design is available from, for example, Science Forum Inc.
It is described in "Very LSI Device Handbook J," published on November 28, 1980, p. 129.

[Problem that the invention seeks to solve]

As a result of studying the above technology, the inventor found the following problem.

Since stray capacitance is added between the wirings or between the wirings and the semiconductor substrate, a signal delay occurs.

An object of the present invention is to effectively reduce wiring capacitance.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this article is as follows.

In other words, either the first layer wiring and the second layer wiring, the second layer wiring and the third layer wiring, or the first layer wiring and the third layer wiring are aligned in the same direction. 6. Stretch it so that it becomes heavy. Allow in-phase signals to propagate.

[Effect]

According to the above means, the capacitance between wirings extending in the same direction, the capacitance between the lower wiring and the wiring in the layer two above, and the capacitance between the upper layer and the semiconductor substrate. Since the capacitance is eliminated, the wiring capacitance can be reduced.

The present invention will be explained below along with examples.

〔Example〕

FIG. 1 is a plan view showing wiring on a semiconductor substrate.

Figure 2 is a sectional view taken along line A-A in Figure 1;
The figure is a wiring model for explaining the signal propagation of the connections g5a and 98 shown in FIG. Note that the glabella insulating film is not shown in FIG. 1 in order to make the wiring configuration easier to see.

In FIGS. 1 and 2, reference numeral 1 denotes a semiconductor substrate made of P-type single crystal silicon. The surface of the semiconductor substrate 1 is covered with a field insulating film 3 made of a silicon oxide film formed by thermal oxidation of the semiconductor substrate 1, and a P-type channel stopper region 2 is formed under the field insulating film 3. For example, 4 is C
The first layer is made of silicon oxide film (SiO2 film) formed by VD.
This is an insulating film of the second layer, and although it is not shown in the figure, one example is CV
The first layer of wiring or electrodes made of a polycrystalline silicon film made of D is covered. Absolute #! A wiring 5 made of a first layer of aluminum film by sputtering, for example, is placed on the lI4.
A plurality of 5a extend parallel to each other. Wiring 5, 5a
Although not shown, is a bipolar transistor or M
It is connected to a clock circuit made up of IS-FETs. For example, deposit SiO on the wiring 5°Sa by CVD.
2 film, phosphosilicate glass (PSG) film, and SiO
It is covered with an insulating film 6 formed by laminating two films in order from the bottom. On the insulating film 6, a plurality of wires 7 made of, for example, a second layer aluminum film formed by sputtering extend in parallel to each other so as to intersect the wires 5.5a. A clock signal and other pulse signals are propagated through the wiring [7]. For example, CVD Nickel s i 02II1.
It is covered with an insulating film 8 formed by laminating a PSG film and a 5if2 film in order from the bottom.

A plurality of wiring lines 9.9a made of a third layer of aluminum film formed by sputtering, for example, extend in parallel to each other on the insulating film 8. Each of the wires 9.9a is connected to a clock circuit formed by a bipolar transistor or an M I S FET.

As shown in FIG. 1, the wiring 9.9a is arranged on the insulating film 8 so as to overlap with the wiring 5.5a.

In other words, the wiring 5.5a is hidden under the arrangement 19.9a. As a result, as described later, those wirings 5
, 5a, and 9.9a are effectively reduced. For example, a SiO2 film or a PSG film formed by CvD is formed to cover the wirings 9 and 9a.

The insulating film 10 is formed by stacking 5iOz films in order from the bottom. A plurality of wiring lines 11 made of, for example, a fourth layer of aluminum film formed by sputtering extend in parallel to each other on the insulating film 10 . The wiring 11 has a layout that overlaps with the wiring 7 and has a layout of a5.5a.

The line width is wider than that of 7.9.9a. Wiring 11
is the power supply potential Vcc, for example 5V, and the circuit ground potential Vss.
For example, it is a power supply wiring for supplying Ov etc. to various circuits on a semiconductor substrate.

Next, using FIG. 3, it will be explained that by forming the wirings 5 and 9 in an overlapping manner, the capacitance added to them is effectively reduced. Wiring 5a.

9a will be explained as an example.

In FIG. 3, S is a clock pulse (hereinafter referred to as a clock pulse).

(simply referred to as a clock) 1, for example, by a bipolar transistor or MISFET,
It is composed of IN+ and IN2 are inverter circuits whose input sides are connected to the clock source S, and whose output sides are connected to the wirings 5a and 9a. The other ends of the wirings 5a and 9a are connected to gates Gs and G* configured by bipolar transistors or MISFETs.

Second, the same phase clocks, that is, the clock pulses Pt and P2, which rise at the same time, fall at the same time, and have the same pulse width, are propagated to the wirings 5a and 9a. As a result, the potential difference between the wirings 415a and 9a is always zero (
0), that is, the stray capacitance between the wirings 5a and 9a is effectively made zero. Further, the stray capacitance formed between the wiring 5a and the uppermost layer wiring 11 is effectively reduced to zero by shielding the wiring 5a with the wiring 9a. The stray capacitance of the wiring 5a is the second p! Only the capacitance formed between the J-th wiring 7 and the semiconductor substrate 1 is formed. therefore.

The capacitance of the wiring 5a is reduced. On the other hand, the capacitance formed between the wiring 9a and the semiconductor substrate 1 is effectively zero because it is shielded by the wiring 5a. Therefore, the stray capacitance of the wiring 9''a is equal to the wiring #!7 of the second layer.
and the capacity configured between.

Finally, only the capacitance is formed between the upper layer arrangement 111 and the upper layer arrangement 111. Therefore, the stray capacitance of the wiring 9a is reduced. The same applies to the wirings 5 other than the wiring 5a and the wirings 9 other than the wiring 9a.

A clock of the same phase is propagated to the wiring 5 and the wiring 9 overlapping the wiring 5, thereby reducing the stray capacitance of the wiring 5.9.

From the above, the propagation speed of the clock propagating through the wirings 5, 5a, 9, and 9a can be increased.

Note that the wiring 11 may be laid out to extend in the same direction as the wirings 5.5a and 9.9a.

Further, the semiconductor integrated circuit device may be laid out so that the wirings 9 and 9a extend in the same direction as the wirings 7 and 11. In this case, the wires 7, 9, -9a are overlapped so that the wire 7 is hidden under the wire 9.9a. In addition, clocks of the same phase are propagated to the wires 7.9 or 9a that are overlapped once. In this way, the stray capacitance between the wiring 7 and 9 or 9a becomes zero. Also, wiring 7
The stray capacitance between the wiring 9.9a and the wiring 811 is made zero by the wiring 9.9a. Also, between the wiring 9.9a and the semiconductor substrate 1,
The stray capacitance of is made zero by the wiring 7.

Furthermore, the semiconductor integrated circuit device may not have the fourth layer of aluminum wiring 11. In this case, the third layer of wiring 9, 9a is at the power supply potential Vcc.

It is used as a power supply wiring for a circuit's ground potential Vss, etc. Therefore, the wiring 9.9a is the other wiring 5.5a.

The wiring is wider than 7. By overlapping the wirings 5, 5a and 7 and extending them in the same direction, and by propagating clocks of the same phase, the wiring capacitance between them can be reduced to zero. The wires 9 and 9a, which are used as power supply wires, are
It may be extended in either the same direction as the wirings 5 and 5a or in a direction intersecting therewith.

The present invention has been specifically explained above using examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in addition to the wiring for powering the clock,
It can also be applied to signal wiring for output signals of logic gates or input signals input to logic gates. In this case, two signal wirings that overlap and extend through an insulating film are
Allow in-phase pulse signals to propagate.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, 4. Stray capacitance of wiring can be effectively reduced. This makes it possible to increase the propagation speed of pulses propagating through the wiring.

[Brief explanation of the drawing]

FIG. 1 is a plan view of wiring on a semiconductor substrate. FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is a model diagram of some wiring. 1... Semiconductor substrate, 2... Channel stopper region,
3...Field insulating film, 4,6.8,10...Insulating film. 5.5a, 7.9.9a, 11... Wiring (aluminum film), S... Signal source, IN... Inverter, G...
・・r 3 Figure 2

Claims (1)

[Claims] 1. First to fourth wirings are laminated on a semiconductor substrate insulated from each other, and the first to third wirings are connected to different circuits, respectively, and are connected to two selected wirings. A semiconductor integrated circuit device in which the first to third wirings are wirings for supplying electric signals to the circuit, and the fourth wiring is wirings for supplying a power supply potential. 1. A semiconductor integrated circuit device characterized in that the wiring is interconnected. 2. The semiconductor integrated circuit device according to claim 1, wherein the lower wiring and the upper wiring, which overlap and extend in the same direction, propagate signals in the same phase.