JPH0286131A - Semiconductor integrated device - Google Patents
Semiconductor integrated deviceInfo
- Publication number
- JPH0286131A JPH0286131A JP23756888A JP23756888A JPH0286131A JP H0286131 A JPH0286131 A JP H0286131A JP 23756888 A JP23756888 A JP 23756888A JP 23756888 A JP23756888 A JP 23756888A JP H0286131 A JPH0286131 A JP H0286131A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- load
- semiconductor integrated
- integrated device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 abstract 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 2
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体集積装置内の電源配線の配線配置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wiring arrangement of power supply wiring within a semiconductor integrated device.
〔従来の技術１
半導体集積装置内の電源配線は、負荷の変動に対する電
源ノイズを防止する為に極力低インピーダンスとする事
が望ましい、この事に対処する従来の技術例を第３図の
ブロック図に示す、第３図において、１は電源端子ＶＤ
Ｄを示す、２は電源端子ＶＳＳ、１５は電源端子１から
負荷までの半導体集積装置内の電源配線を示す、１６は
電源端子２から負荷までの半導体集積装置内の電源配線
を示す、前述した電源ノイズを防止する電源配線の低イ
ンピーダンス化の為に、電源配線の断面積を大きくする
必要から電源端子から負荷までの電源配線１５と１６を
出来る丈幅広くしている。[Prior art 1] It is desirable that the impedance of the power supply wiring in a semiconductor integrated device be as low as possible in order to prevent power supply noise due to load fluctuations. An example of a conventional technology for dealing with this is shown in the block diagram of Fig. 3. 3, 1 is the power supply terminal VD
2 indicates the power supply terminal VSS, 15 indicates the power supply wiring within the semiconductor integrated device from the power supply terminal 1 to the load, and 16 indicates the power supply wiring within the semiconductor integrated device from the power supply terminal 2 to the load, as described above. In order to reduce the impedance of the power wiring to prevent power noise, it is necessary to increase the cross-sectional area of the power wiring, so the power wiring 15 and 16 from the power terminal to the load are made as wide as possible.
従来技術の他の例を第４図のブロック図に示す、１は電
源端子ＶＤＤを示す、２は電源端子ＶＳＳを示す、１７
．１８．１９．２０は電源端子ＶＤＤ １から各負荷へ
つながる１ｆ源配線を示し、それぞれ独立して電源端子
１から各負荷へ接続されている。２１．２２．２３．２
４は電源端子■ＳＳ２から各負荷へつながる電源配線を
示し、それぞれ独立して電源端子２から各負荷へ接続さ
れている。第４図の従来例では、電源ノイズを防止する
為に、各負荷への電源配線を独立させた事により、例え
ば負荷１に於ける負荷変動による電源ノイズが、他の負
荷２、負荷３、負荷４に影響な与＾ないようにしている
。Another example of the prior art is shown in the block diagram of FIG. 4, where 1 indicates the power supply terminal VDD, 2 indicates the power supply terminal VSS, 17
．． Reference numerals 18, 19, and 20 indicate 1f source wires connected from the power supply terminal VDD 1 to each load, which are each independently connected from the power supply terminal 1 to each load. 21.22.23.2
Reference numeral 4 indicates a power supply wiring connected from the power supply terminal SS2 to each load, which is independently connected from the power supply terminal 2 to each load. In the conventional example shown in Fig. 4, in order to prevent power supply noise, the power supply wiring to each load is made independent, so that, for example, power supply noise due to load fluctuations in load 1 is transmitted to other loads 2, 3, etc. I try not to have any effect on load 4.
［発明が解決しようとする課題］
しかし前述の従来例の場合は、以下に示す問題点がある
。[Problems to be Solved by the Invention] However, the above-mentioned conventional example has the following problems.
前述の第３図の場合は、電源配線１５と１６を出来る丈
幅広くする必要があるが、高周波の負荷を駆動する場合
は、前記電源型！８１５と１６の幅は１１００ＬＬ程度
必要となり、この事は数ミリ・メートル角以下のサイズ
の半導体集積装置の場合には面積巾約３割を占めるに至
り、半導体集積装置のコストを高くしてしまう問題点が
有る。In the case of the above-mentioned FIG. 3, it is necessary to make the power supply wirings 15 and 16 as wide as possible, but when driving a high frequency load, the power supply wiring type 15 and 16 must be made as wide as possible. The width of 815 and 16 is required to be about 1100 LL, which accounts for about 30% of the area width in the case of a semiconductor integrated device with a size of several millimeters square or less, increasing the cost of the semiconductor integrated device. There are problems.
前述の第４図の場合は、電源配線が負荷の数だけ必要と
なるので、電源配線数が増＾てしまい、この事は半導体
集積装置の面積を太きくシ、第３図の場合と同様にコス
トを高くしてしまう問題点がある。In the case of Fig. 4 mentioned above, the number of power supply wirings increases because the number of power supply wirings is equal to the number of loads, and this increases the area of the semiconductor integrated device, as in the case of Fig. 3. However, there is a problem in that it increases the cost.
本発明は上述の問題点を解決するものであり、その目的
とする所は、低コストで、電源ノイズに強い半導体集積
装置の電源配線配置を提供するものである。The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a power supply wiring arrangement for a semiconductor integrated device that is low in cost and resistant to power supply noise.
〔課題を解決するための手段１
上述した問題点を解決するため、本発明は配線層を二つ
以上有する半導体集積装置に於いて、第１の配線層の上
に、少なくとも他の配線層のうちのひとつの第２の配線
層の全体もしくは一部を重ねて配線し、前記第１の配線
層と前記第２の配線層とは同電位の電源である事を特徴
とする。[Means for Solving the Problems 1] In order to solve the above-mentioned problems, the present invention provides, in a semiconductor integrated device having two or more wiring layers, at least another wiring layer on top of the first wiring layer. All or part of one of the second wiring layers is overlaid and wired, and the first wiring layer and the second wiring layer are powered by the same potential.
１作 用］
本発明によれば、電源配線を第１の配線層と、少なくと
も他の配線層のうちのひとつの第２の配線層とを重ねて
配線するので、電源配線の断面積が大きくなり、従って
低インピーダンスである。1 Effect] According to the present invention, since the power supply wiring is routed by overlapping the first wiring layer and the second wiring layer, which is at least one of the other wiring layers, the cross-sectional area of the power supply wiring is large. Therefore, it has low impedance.
また、厚み方向に電源配線の断面積を大きくするので、
半導体集積装置の面積増加には影響しない。Also, since the cross-sectional area of the power supply wiring is increased in the thickness direction,
It does not affect the increase in area of the semiconductor integrated device.
［実 施 例］
以下に本発明の詳細な説明する。第１図は本発明の一実
施例を示すブロック図であり、配線層を２つ有する半導
体集積装置の例である。ｌは電源端子ＶＤＤ、２は電源
端子ＶＳＳ、３は半導体集積装置内の電源配線で、電源
端子ＶＤＤＩから各負荷へ一層目の配線層を用いて接続
されている。４は電源配線１の上に平行して配線された
電源配線で、二層目の配線層を用いている。５は半導体
集積装置内の電源配線で、電源端子ＶＳＳ２から各負荷
へ一層目の配線層を用いて接続されている。６は電源配
線５の上に平行して配線された電源配線で、二層目の配
線層を用いている０通常−層目の配線層と二層目の配線
層は酸化シリコン（Ｓ ｉ Ｏ，）によって絶縁されて
いるが、電源配線３と電源配線４とが重なっている所は
、前記酸化シリコンを開口させ、電源配置３と電源型Ｉ
Ｉ４とは接合されている。１ｆ源配！８５と電源型ＩＪ
ｉｅとも、上記電源配線３と電源配線４の関係と同様に
接合されている。[Example] The present invention will be described in detail below. FIG. 1 is a block diagram showing one embodiment of the present invention, and is an example of a semiconductor integrated device having two wiring layers. 1 is a power supply terminal VDD, 2 is a power supply terminal VSS, and 3 is a power supply wiring within the semiconductor integrated device, which is connected from the power supply terminal VDDI to each load using the first wiring layer. Reference numeral 4 denotes a power supply wiring that is wired in parallel on top of the power supply wiring 1, using a second wiring layer. Reference numeral 5 denotes a power supply wiring within the semiconductor integrated device, which is connected from the power supply terminal VSS2 to each load using the first wiring layer. Reference numeral 6 denotes a power supply wiring wired in parallel on the power supply wiring 5, and the second wiring layer is used.The 0th normal wiring layer and the second wiring layer are made of silicon oxide (SiO , ), but the silicon oxide is opened where the power supply wiring 3 and the power supply wiring 4 overlap, and the power supply arrangement 3 and the power supply type I
It is connected to I4. 1f source! 85 and power type IJ
ie are also connected in the same manner as the relationship between the power supply wiring 3 and the power supply wiring 4 described above.
負荷１、負荷２、負荷３、負荷４は半導体集積装置内の
機能別区分を表わしている０例えば時計用半導体集積装
置であれば、負荷１は発振回路部、負荷２は分周回路部
、負荷３は出力回路部、負荷４は制御回路部といった区
分を表わしている。Load 1, load 2, load 3, and load 4 represent functional divisions within a semiconductor integrated device.For example, in a semiconductor integrated device for a watch, load 1 is an oscillation circuit section, load 2 is a frequency division circuit section, The load 3 represents the output circuit section, and the load 4 represents the control circuit section.
第１図では、二層目の配線層は一層目配線層の大きさに
納まる形で幅が狭く書かれているが、二層目の配線層が
一層目の配線層よりも幅が広い場合でも、無論同じ効果
が得られる。In Figure 1, the width of the second wiring layer is narrow so that it fits within the size of the first wiring layer, but if the width of the second wiring layer is wider than the first wiring layer. However, the same effect can be obtained.
本発明の他の実施例を第２図のブロック図に示す、第２
図も配線層を２つ有する半導体集積装置の例である。ｌ
は電源端子ＶＤＤ、２は電源端子ＶＳＳ、７は電源端子
ＶＤＤＩから負荷ｌまで一層目の配線層で接続した電源
配線。８は電源端子ＶＤＤ ｌから負荷２まで二層目の
配線層で接続した電源配線。９は電源端子ＶＤＤｌから
負荷３まで一層目の配線層で接続した電源配線、１０は
電源端子ＶＤＤ ｌから負荷４まで二層目の配線層で接
続した電源配線、１１．１２．１３．１４は電源端子Ｖ
ＳＳ２から各負荷へ接続する電源配線で、１１は一層目
の配線層で負荷ｌへ、１２は二層目の配線層で負荷２へ
、１３は一層目の配線層で負荷３へ、１４は二層目の配
線層で負荷４へ、それぞれ独立して接続されている。電
源配線７と８、電源配線９と１０、電源配線１１と１２
、電源配線１３と１４は、各々可能な限り、上下方向に
重なり平行に配線されている。Another embodiment of the present invention is shown in the block diagram of FIG.
The figure also shows an example of a semiconductor integrated device having two wiring layers. l
is the power supply terminal VDD, 2 is the power supply terminal VSS, and 7 is the power supply wiring connected from the power supply terminal VDDI to the load 1 on the first wiring layer. 8 is the power supply wiring connected from the power supply terminal VDD l to the load 2 on the second wiring layer. 9 is the power supply wiring connected from the power supply terminal VDDl to the load 3 on the first wiring layer, 10 is the power supply wiring connected from the power supply terminal VDDl to the load 4 on the second wiring layer, 11.12.13.14 is the power supply wiring connected on the second wiring layer from the power supply terminal VDDl to the load 4. Power terminal V
In the power supply wiring connecting SS2 to each load, 11 is the first wiring layer to load 1, 12 is the second wiring layer to load 2, 13 is the first wiring layer to load 3, and 14 is the first wiring layer to load 1. They are each independently connected to the load 4 on the second wiring layer. Power wiring 7 and 8, power wiring 9 and 10, power wiring 11 and 12
, the power supply wirings 13 and 14 are wired in parallel to each other, overlapping each other in the vertical direction as much as possible.
［発明の効果］
以上述べたように発明によれば、第一の配線層の上に他
の配線層を重ねて電源配線を行うので、電源配線の線幅
を、−層だけの配線層を用いた電源配線に比べて、幅広
くする必要がなく、半導体集積装置のサイズが小さくで
き、低コストで製造できる。[Effects of the Invention] As described above, according to the invention, power supply wiring is performed by overlapping another wiring layer on top of the first wiring layer, so that the line width of the power supply wiring can be reduced by reducing the width of the wiring layer by only -layers. Compared to the power supply wiring used, there is no need to make it wider, the size of the semiconductor integrated device can be reduced, and it can be manufactured at low cost.
また、電源配線が、上下２つの配線層で行うので、電源
配線の低インピーダンス化が可能となり、ノイズに強く
、高周波用に適した電源配線として使用できる。Furthermore, since the power supply wiring is formed in two wiring layers, the upper and lower wiring layers, it is possible to reduce the impedance of the power supply wiring, which is resistant to noise and can be used as a power supply wiring suitable for high frequency applications.
また、半導体集積装置内の電源配線は一般に、アルミ材
を用いて行うが、半導体集積装置内に有って、一番熱伝
導率の良いのは前述のアルミ材である。従って、電源配
線（アルミ）を上下２つの配線層で行う事により、半導
体集積装置内で発生する熱を外部へ発散し易（なり、半
導体集積装置の安定動作にも寄与する。Furthermore, power supply wiring within a semiconductor integrated device is generally made of aluminum, and the above-mentioned aluminum material has the best thermal conductivity within a semiconductor integrated device. Therefore, by providing the power supply wiring (aluminum) in two wiring layers, upper and lower, the heat generated within the semiconductor integrated device can be easily dissipated to the outside, which also contributes to stable operation of the semiconductor integrated device.
また、半導体集積装置はアルミ材が湿気によって腐食す
るという欠点があるが、電源配！（アルミ）を上下２つ
の配線層で行う事により、上側の配線層は下側の配線層
を湿気から保護する形となり、信頼性の向上にも寄与す
る。In addition, semiconductor integrated devices have the disadvantage that the aluminum material corrodes due to moisture, but power supply wiring! By using aluminum (aluminum) in two wiring layers, the upper wiring layer protects the lower wiring layer from moisture, which also contributes to improved reliability.
第１図は本発明の一実施例を示すブロック図。 第２図は本発明の他の実施例を示すブロック図。 第３図は従来技術の一実施例を示すブロック図。 第４図は従来技術の他の実施例を示すブロック図。 １・・・・・電源端子ＶＤＤ ２・・・・・電源端子ＶＳＳ ３、５ ・ ・ ・ ４、６ ・ ・ ・ ７、９、１１ ８、１０、１ １５、 ｌ ６． ２１、２２、 一層目の配線層の電源配線 二層目の配線層の電源配線 、１３ 一層目の配線層の電源配線 ２．１４ 二層目の配線層の電源配線 １７．１８．１９．２０ 電源配線 ２３．２４ 電源配線 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 上 柳 雅 誉（他１名）第１図 第 図 第 図 FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing another embodiment of the present invention. FIG. 3 is a block diagram showing an embodiment of the prior art. FIG. 4 is a block diagram showing another embodiment of the prior art. 1...Power supply terminal VDD 2...Power supply terminal VSS 3, 5 ・ ・ ・ 4, 6 ・ ・ ・ 7, 9, 11 8, 10, 1 15, l 6. 21, 22, Power supply wiring on the first wiring layer Power supply wiring for the second wiring layer , 13 Power supply wiring on the first wiring layer 2.14 Power supply wiring for the second wiring layer 17.18.19.20 power wiring 23.24 power wiring that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Homare Kamiyanagi (and 1 other person) Figure 1 No. figure No. figure
Claims (1)
配線層の上に、少なくとも他の配線層のうちのひとつの
第２の配線層の全体もしくは一部を重ねて配線し、前記
第１の配線層と前記第２の配線層とは同電位の電源配線
である事を特徴とする半導体集積装置。In a semiconductor integrated device having two or more wiring layers, the entire or part of a second wiring layer of at least one of the other wiring layers is overlaid on the first wiring layer, and the A semiconductor integrated device characterized in that the first wiring layer and the second wiring layer are power supply wirings having the same potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23756888A JPH0286131A (en) | 1988-09-22 | 1988-09-22 | Semiconductor integrated device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23756888A JPH0286131A (en) | 1988-09-22 | 1988-09-22 | Semiconductor integrated device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0286131A true JPH0286131A (en) | 1990-03-27 |
Family
ID=17017242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23756888A Pending JPH0286131A (en) | 1988-09-22 | 1988-09-22 | Semiconductor integrated device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0286131A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02284448A (en) * | 1989-04-26 | 1990-11-21 | Toshiba Corp | Semiconductor device |
| JPH0653211A (en) * | 1991-01-22 | 1994-02-25 | Nec Corp | Resin-sealed semiconductor integrated circuit |
| EP0887800A2 (en) * | 1997-06-25 | 1998-12-30 | Honeywell Inc. | Power distribution system for semiconductor die |
-
1988
- 1988-09-22 JP JP23756888A patent/JPH0286131A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02284448A (en) * | 1989-04-26 | 1990-11-21 | Toshiba Corp | Semiconductor device |
| JPH0653211A (en) * | 1991-01-22 | 1994-02-25 | Nec Corp | Resin-sealed semiconductor integrated circuit |
| EP0887800A2 (en) * | 1997-06-25 | 1998-12-30 | Honeywell Inc. | Power distribution system for semiconductor die |
| EP0887800A3 (en) * | 1997-06-25 | 1999-07-14 | Honeywell Inc. | Power distribution system for semiconductor die |
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