JPH03263355A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03263355A JPH03263355A JP6302290A JP6302290A JPH03263355A JP H03263355 A JPH03263355 A JP H03263355A JP 6302290 A JP6302290 A JP 6302290A JP 6302290 A JP6302290 A JP 6302290A JP H03263355 A JPH03263355 A JP H03263355A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer signal
- potential
- signal wiring
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 abstract description 34
- 230000008878 coupling Effects 0.000 abstract description 8
- 238000010168 coupling process Methods 0.000 abstract description 8
- 238000005859 coupling reaction Methods 0.000 abstract description 8
- 239000011229 interlayer Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に配線間のカップリ
ング容量により発生するノイズの防止構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a structure for preventing noise caused by coupling capacitance between wiring lines.
従来、例えば半導体基板上に形成された電位が異なる信
号配線が交差する箇所は、第４図（ａ）（ｂ）に示すよ
うに、下層信号配線３と上層信号配線５の間に眉間絶縁
膜４のみを有するｍ造となっていた。このため、２つの
配線間に、眉間絶縁膜の厚さｄと面積Ｓと定数εからな
るカップリング容ｆｉＣ（Ｃ＝ｅＳ／ｄ）が存在してい
た。Conventionally, for example, where signal lines formed on a semiconductor substrate with different potentials intersect, an insulating film is placed between the lower layer signal line 3 and the upper layer signal line 5 between the lower layer signal line 3 and the upper layer signal line 5, as shown in FIGS. It was of m construction with only 4. Therefore, a coupling capacitance fiC (C=eS/d) consisting of the thickness d of the glabella insulating film, the area S, and the constant ε existed between the two wirings.
上述したように従来の半導体集積回路では、信号配線が
交差する箇所は一定膜厚の眉間絶縁膜が形成された構造
となっていたため、一方の信号配線の電位変化が大きい
時に、配線間のカップリング容量が影響して、他方の信
号配線にノイズを発生させていた。このため、このノイ
ズが、回路の誤動作や動作速度の遅延の原因となり、半
導体集積回路の信頼性を低下させるという問題点かあっ
た。As mentioned above, in conventional semiconductor integrated circuits, a glabella insulating film of a constant thickness is formed at the intersection of signal wires, so when the potential change of one signal wire is large, a cup between the wires may occur. The ring capacitance was causing noise in the other signal wiring. Therefore, this noise causes a malfunction of the circuit and a delay in the operating speed, resulting in a problem of lowering the reliability of the semiconductor integrated circuit.
第１の発明の半導体集積回路は、半導体基板上に形成さ
れた下層配線と、この下層配線上に絶縁膜を介して形成
され下層配線と交差する上層配線とを有する半導体集積
回路において、前記下層配線と前記上層配線間にシール
ド用配線を設けたものである。A semiconductor integrated circuit according to a first aspect of the invention includes a lower layer wiring formed on a semiconductor substrate, and an upper layer wiring formed on the lower layer wiring with an insulating film interposed therebetween and crossing the lower layer wiring. A shield wiring is provided between the wiring and the upper layer wiring.
第２の発明の半導体集積回路は、電位が印加される半導
体基板と、この半導体基板上に絶縁膜を介して形成され
た配線とを有する半導体集積回路において、前記半導体
基板と前記配線間にシールド用配線を設けたものである
。A semiconductor integrated circuit according to a second aspect of the invention includes a semiconductor substrate to which a potential is applied and wiring formed on the semiconductor substrate via an insulating film, in which a shield is provided between the semiconductor substrate and the wiring. It is equipped with wiring for use.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の上面図
及びＡ−Ａ’線断面図であり、上面図は配線のみを示し
ている。FIGS. 1(a) and 1(b) are a top view and a sectional view taken along the line AA' of a first embodiment of the present invention, and the top view shows only the wiring.
第１図（ａ）、（ｂ）において、半導体基板１上に形成
された酸化膜２上には下層信号配線３が形成され、その
上部にはこの下層信号配線３に交差するように上層信号
配線５が形成されているが、特にこの下層信号配線３と
上層信号配線５の交差する間には、眉間絶縁膜４Ａ、４
Ｂに覆われ一定電位が印加されるシールド用配線６が形
成されている。In FIGS. 1(a) and 1(b), a lower layer signal wiring 3 is formed on an oxide film 2 formed on a semiconductor substrate 1, and an upper layer signal wiring 3 is formed above the lower layer signal wiring 3 so as to cross this lower layer signal wiring 3. A wiring line 5 is formed, and especially between the intersections of the lower layer signal wiring line 3 and the upper layer signal wiring line 5, glabella insulating films 4A, 4 are formed.
A shield wiring 6 is formed which is covered with B and to which a constant potential is applied.
このように構成された第１の実施例によれば、下層信号
配線３と上層信号配線５との間にシールド用配線６が設
けられているため、上層及び下層の信号配線間には直接
容量が存在しなくなり、シールド用配線６が一定電位で
あるため、例えば上層信号配線５の電位が大きく変化し
ても、その影響はシールド用配線６に吸収される。その
ため、下層信号配線３には影響が及ぶことがないのでノ
イズは発生しない。According to the first embodiment configured in this way, since the shield wiring 6 is provided between the lower layer signal wiring 3 and the upper layer signal wiring 5, there is a direct capacitance between the upper layer and lower layer signal wiring. is no longer present, and the shield wiring 6 is at a constant potential, so even if the potential of the upper layer signal wiring 5 changes significantly, for example, the effect is absorbed by the shield wiring 6. Therefore, since the lower layer signal wiring 3 is not affected, no noise is generated.
第２図（ａ）、（ｂ）は本発明の第２の実施例の上面図
及びＢ−Ｂ’線断面図である。FIGS. 2(a) and 2(b) are a top view and a sectional view taken along the line BB' of a second embodiment of the present invention.
第２図（ａ）、（ｂ）において、電位が印加される半導
体基板ＩＡ上には酸化膜２を介してシールド用配線６が
形成されており、このシールド用配線６上には眉間絶縁
膜４を介して信号配線５Ａが形成されている。In FIGS. 2(a) and 2(b), a shield wiring 6 is formed through an oxide film 2 on the semiconductor substrate IA to which a potential is applied, and a glabella insulating film is formed on this shield wiring 6. A signal wiring 5A is formed through the wire 4.
このように構成された第２の実施例によれば、半導体基
板ＩＡの電位が大きく変化しても信号配線５Ａとの間に
シールド用配線６が設けられているため、基板電位との
カップリング容量はシールド用配線６との間に生じるだ
けで、信号配線５Ａに影響は及ぶことがないため、ノイ
ズは発生しない。According to the second embodiment configured in this way, even if the potential of the semiconductor substrate IA changes significantly, the shielding wiring 6 is provided between the signal wiring 5A and the coupling with the substrate potential. Since the capacitance is only generated between the shield wiring 6 and the signal wiring 5A, no noise is generated.
第３図（ａ＞、（ｂ）は本発明の第３の実施例の上面図
及びｃ−ｃ’線断面図であり、本発明をインバータ回路
を有する半導体集積回路に適用した場合を示している。FIGS. 3(a) and 3(b) are a top view and a sectional view taken along the line c-c' of a third embodiment of the present invention, showing a case where the present invention is applied to a semiconductor integrated circuit having an inverter circuit. There is.
パッド１０からの入力信号配線９が、電源配線７と交差
している場合、電源配線７の電位が変化すると、下を通
る入力信号配線９との間のカップリング容量が作用して
、入力信号にノイズが発生する。そこで、これらの間に
ＧＮＤ電位シールド用配線８を設けることにより、電源
配線７とのカップリング容量は、シールド用配線との間
に生じるだけで入力信号配線９には、電源配線７の電位
の変化は影響しない。従って入力初段インバータ１２の
出力配置！１３に出力される信号は常に正常なものとな
る。また、シールド配線をＧＮＤ （接地）レベルとす
るため、入力信号配線９はＧＮＤ電位とのカップリング
容量をもつ。そのため、ＧＮＤ電位に対する入力電位の
電位差を同じように保つことができる。When the input signal wiring 9 from the pad 10 crosses the power supply wiring 7, when the potential of the power supply wiring 7 changes, the coupling capacitance between the input signal wiring 9 passing below acts and the input signal Noise is generated. Therefore, by providing the GND potential shielding wiring 8 between these, the coupling capacitance with the power supply wiring 7 is generated only between the shielding wiring and the input signal wiring 9 is connected to the potential of the power supply wiring 7. Change has no effect. Therefore, the output arrangement of the input first stage inverter 12! The signal output to 13 is always normal. Furthermore, since the shield wiring is at the GND (ground) level, the input signal wiring 9 has a coupling capacitance with the GND potential. Therefore, it is possible to maintain the same potential difference between the input potential and the GND potential.
以上説明したように本発明は、交差する配線の間または
電位が印加される基板と配線との間に一定電位を保つシ
ールド用配線を設けることにより、カップリング容量に
よるノイズの発生を防ぐことができるため、半導体集積
回路の信頼性を向上させることができるという効果があ
る。As explained above, the present invention prevents the generation of noise due to coupling capacitance by providing a shielding wiring that maintains a constant potential between wirings that intersect or between a substrate and wiring to which a potential is applied. Therefore, there is an effect that the reliability of the semiconductor integrated circuit can be improved.
第１図（ａ）、（ｂ） 〜第３図（ａ）、（ｂ）は本発
明の第■〜第３の実施例の上面図及び断面図、第４図（
ａ）、（ｂ）は従来例の上面図及び＝６
断面図である。
１− ＩＡ・・・半導体基板、２・・・酸化膜、３・・
下層信号配線、４．４Ａ、４Ｂ・・・層間絶縁膜、５・
・・上層信号配線、６・・・シールド用配線、７・・・
電源配線、８・・・ＧＮＤ電位シールド用配線、９・・
・入力信号配線、１０・・パッド、１１・・・ＧＮＤ配
線、１２・・・入力初段インバータ、１３・・・出力配
線。FIGS. 1(a), (b) to 3(a), (b) are top views and cross-sectional views of the third embodiment of the present invention, and FIG.
a) and (b) are a top view and a =6 sectional view of the conventional example. 1-IA...Semiconductor substrate, 2...Oxide film, 3...
Lower layer signal wiring, 4.4A, 4B... interlayer insulating film, 5.
... Upper layer signal wiring, 6... Shield wiring, 7...
Power supply wiring, 8...GND potential shield wiring, 9...
- Input signal wiring, 10... Pad, 11... GND wiring, 12... Input first stage inverter, 13... Output wiring.
Claims (1)
線上に絶縁膜を介して形成され下層配線と交差する上層
配線とを有する半導体集積回路において、前記下層配線
と前記上層配線間にシールド用配線を設けたことを特徴
とする半導体集積回路。 ２、電位が印加される半導体基板と、この半導体基板上
に絶縁膜を介して形成された配線とを有する半導体集積
回路において、前記半導体基板と前記配線間にシールド
用配線を設けたことを特徴とする半導体集積回路。[Claims] 1. In a semiconductor integrated circuit having a lower layer wiring formed on a semiconductor substrate and an upper layer wiring formed on the lower layer wiring with an insulating film interposed therebetween and crossing the lower layer wiring, the lower layer wiring and A semiconductor integrated circuit characterized in that a shield wiring is provided between the upper layer wirings. 2. A semiconductor integrated circuit having a semiconductor substrate to which a potential is applied and wiring formed on the semiconductor substrate via an insulating film, characterized in that a shielding wiring is provided between the semiconductor substrate and the wiring. Semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6302290A JPH03263355A (en) | 1990-03-13 | 1990-03-13 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6302290A JPH03263355A (en) | 1990-03-13 | 1990-03-13 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03263355A true JPH03263355A (en) | 1991-11-22 |
Family
ID=13217282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6302290A Pending JPH03263355A (en) | 1990-03-13 | 1990-03-13 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03263355A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6380567B1 (en) | 1998-02-02 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
-
1990
- 1990-03-13 JP JP6302290A patent/JPH03263355A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6380567B1 (en) | 1998-02-02 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and fabrication method thereof |
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