JPH0348455A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to lessen a transfer lag due to a long-distance wiring and to improve the operating speed of a semiconductor device by a method wherein signal wirings, which are electrically driven in the same phase, are arranged in parallel to each other. CONSTITUTION:A drive circuit 104 and another drive circuit 105 make a signal of the same phase output. Moreover, a signal wiring 102 for transferring an output signal of the circuit 104 to a passive circuit 106 and other signal wiring 103 for transferring an output signal of the circuit 105 to other passive circuit 107 are arranged in parallel to each other holding a fixed interval. As the circuits 104 and 105 output the signal of the same phase, the time constants of these circuits 104 and 105 are greatly decreased. That is, a transfer lag is decreased. In particular, when the micronization of a wiring progresses and a Calpha becomes small, the thickness of a wiring layer can not be made small so much. Therefore, a Cbeta relatively becomes large and the reduced effect of the transfer lag is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a wiring method on a semiconductor device.

[Conventional technology]

In conventional semiconductor devices, the output of one drive circuit (an electrical circuit that outputs an arbitrary signal and drives the signal wiring) is connected to multiple passive circuits (an electrical circuit that receives signals from the signal wiring) via signal wiring. input). FIG. 2(a) illustrates a simple case. In the figure, 4 is a drive circuit, and 6 and 7 are passive circuits. At this time, the signal wiring 2 has a parasitic capacitance as shown in FIG. 2(b). In the figure, C. is the bottom capacitance to the board, and C is the side capacitance to the board. This situation is shown as a circuit diagram in FIG. 2(C). Further, an electrical equivalent circuit is shown in FIG. 2(d). In the figure, R and CD are the internal resistance and output capacitance of the drive circuit 4, and Co is the input capacitance of the passive circuits 6 and 70.

[Problem to be solved by the invention]

The time constant τ of signal transmission from the drive circuit to the passive circuit of the conventional semiconductor device described above is calculated as =R, as is clear from the equivalent circuit in Fig. 2(d), considering the parasitic capacitance attached to the signal wiring.
(CD+C-+2Cs+2Co). Decomposing the time constant τ = RCD + R (C + 2Cj) + R・2Co
becomes. When the wiring becomes long, the parasitic capacitance of the wiring increases, and τ becomes thicker due to the second term. For this reason, R
However, R is the internal resistance of the drive circuit, and in order to reduce this, it is necessary to increase the drive capability. However, in the case of a normal MOST, CD increases in order to reduce R, and problems such as through current occur unless the drive circuit in the previous stage is also enlarged. Therefore, in the conventional case, there is a limit to reducing the transmission delay due to long-distance wiring, and there is a drawback that it is difficult to improve the operating speed of the semiconductor device.

[Means to solve the problem]

The present invention provides a semiconductor device in which signal wiring for transmitting an output signal of a drive circuit to a passive circuit is provided on a semiconductor substrate. This includes other signal wirings that are supplied with output signals and are arranged in parallel with the signal wirings.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1(a) is a layout diagram of an embodiment of the present invention.

101 is a semiconductor device, 104 is a drive circuit, 105 is another drive circuit, and 104 and 105 output signals in the same phase.

102 is a signal wiring that transmits the output signal of the drive circuit 104 to the passive circuit 106; 103 is another signal wiring that transmits the output signal of another drive circuit 105 to the passive circuit 107; are arranged in parallel.

FIG. 1(b) is a cross-sectional view of the semiconductor chip taken along the line AA' in FIG. 1(a). Signal wiring 102,1
03 has a parasitic capacitance to the semiconductor substrate 108 and an inter-wiring capacitance.

FIG. 1(c) shows a classification of parasitic capacitances. 0 here
0 is the capacitance between wires, C. is the bottom capacitance to the board, and C is the side capacitance to the board. As shown, one of the side capacitances of the signal wiring becomes a coupling capacitance with the other of the wiring pair, and the capacitance to the substrate is reduced compared to the case of a single wiring. This situation is shown as a circuit diagram in FIG. 1(b) and as an equivalent circuit in FIG. 1(e).

As described above, since the drive circuits 104 and 105 output signals in the same phase, the time constant τ of this circuit. is τ.

”R (CD 10, + Cβ+CO), and the influence of C0 is removed.Compared with the time constant τ in the conventional case, Δr=R(CD+C.+2Ca+2Co)
R(Co+C, 10C.s+Co)=R(Cβ10.

), and the time constant has decreased significantly. That is, the transmission delay becomes smaller. In particular, as wiring becomes finer and C6 becomes smaller, the thickness of the wiring layer cannot be made much smaller, so Cβ becomes relatively larger and the transmission delay reduction effect of the present invention becomes greater.

FIG. 3 is a layout diagram of a modification of one embodiment of the present invention.

One of the wiring pairs is a dummy wiring that does not input to the passive circuits 206 and 207. The drive circuits 204 and 205 operate in the same phase as in the embodiment (1). A circuit diagram and an equivalent circuit diagram in this case are shown in FIGS. 3(b) and 3(c), respectively.

However, C s '' C o + C , + C s , and although the influence of line capacitance #co is not completely eliminated, the time constant is smaller than in the conventional example, and the propagation delay is reduced.

When providing dummy wiring as in the above-mentioned modification, the fourth
As shown in Figure (a), this is more effective when the wiring is multilayered.

FIG. 4(a) is a sectional view of a wiring portion showing another modification.

Signal wirings 202 and 203 are arranged in close proximity and formed in multiple layers.

Passive circuits 206 and 207 are connected to the signal wiring 203. FIG. 4(b) shows how the parasitic capacitance is generated in this case.

FIG. 4(c) shows an equivalent circuit in this case. Signal wiring 2
Since the side volume 1kcs' of 03 is smaller than that of C,
Since it can be ignored along with the bottom surface capacitance, the time constant τ becomes smaller by that amount than in the case of the above-mentioned modification. However, C+=CD+2Co, C2=C. +2Cs+Cn
, C 3 = C c.

FIG. 5 shows another embodiment of the present invention. This embodiment is a read-only memory (ROM), and a plan view of the chip thereof is shown as 500 in FIG. 5(a). The 17-bit address signal is supplied to address buffers AO to A16 of chip 500, and each buffer supplies the true complement of the corresponding address signal to decoder 502. Decoder 502 responds to the supplied address signal to select a predetermined RO in ROM cell array 501.
Select M cell. In this embodiment, 16 ROM cells are selected for one address information. selected R
The stored data of the OM cell is amplified by the sense amplifier 503 and output from the 16 output buffers 00 to 015 to the outside of the chip 500. In addition, for the sake of simplicity of the drawing, the address person Kahaffa A, the dehood 502, the cell array 50l, the sense amplifier 503, and the output haffa O
The wiring between them is omitted.

The ROM chip 500 further includes a chip enable buffer 550 (CE) and an output enable buffer 560 (
A chip enable signal and an output enable signal are supplied from the outside. The chip enable signal enables the ROM chip 500, takes in an address signal, and activates the internal circuit.

Therefore, the output of chip enable buffer 550 is transferred to address buffers AO to A16 via wiring 510. Address person buffer A as shown
Since O to A16 are arranged along the periphery of the chip 500, the wiring 510 becomes very long. Therefore, according to the present invention, the chip enable buffer 550
A signal having the same phase as the chip enable signal transferred to the wire 510 is further output, and the same signal is supplied to a second wire 511 provided in parallel with the wire 510.

FIG. 5(b) shows a logic circuit diagram of the chip enable buffer 550. A terminal 551 is a terminal for supplying a chip enable signal from the outside, and is connected to the wiring 510 via four inverters 552 to 555. The connection point between inverters 553 and 554 is two inverters 556
, 557 to the second wiring 511.

Therefore, signals of the same phase are obtained on the wirings 510 and 511.

The output enable signal supplied to the output enable buffer 560 controls the output timing of read data in the chip enable state. Therefore, the wiring 51 from the chip enable buffer 550
The output buffers 00 to 01 receive the chip enable signal via 0 and take in the output enable signal from the outside.
Transfer to 5. Output buffers OO to 015 are also chip 5
It is provided along the periphery of 00. Therefore, the wiring 520 for transferring the output of the buffer 560 also becomes quite long. Therefore, according to the present invention, a second wiring 521 is provided in parallel with the wiring 520, and the output enable buffer 560 supplies a signal in phase with the signal to the wiring 520 to the second wiring 521. As shown in FIG. 5C, the output enable buffer 560 has a terminal 561 to which an output enable signal is supplied from the outside, and the terminal is supplied to one input of a two-input NOR gate 562. A chip enable signal is supplied to the other input via wiring 510. The output of NOR gate 562 is connected to three inverters 5
It becomes a transfer signal to the wiring 520 via 63, 566, and 567. The output of the inverter 563 further passes through two inverters 564 and 565 to become a drive signal for the wiring 521.

In this way, the internal chip enable signal transfer wiring 51
0 and the internal output enable signal transfer wiring 520 are long, but according to the present invention, the second wiring 520 is connected in parallel with each other.
11.521 is provided, and in-phase signals are supplied. Therefore, the effective parasitic capacitance of the wirings 5lO and 520 is reduced, and the signal transmission delay is correspondingly reduced.

〔Effect of the invention〕

As explained above, the present invention provides signal wiring that is electrically driven in the same phase by arranging them in parallel and close together.
By sharing a portion of the parasitic capacitance in signal wiring, it is possible to effectively reduce parasitic capacitance, reduce transmission delays associated with long-distance wiring, and improve the operating speed of semiconductor devices. be.

[Brief explanation of drawings]

FIG. 1(a) is a layout diagram of an embodiment of the present invention, FIG. 1(b)
) is a cross-sectional view of the semiconductor chip taken along the line A-A' in FIG. 1(a), FIG. ) is a circuit diagram of one embodiment, FIG. 1(e) is an equivalent circuit diagram of one embodiment, and FIG. 2(
a), (b), (c) and (d) are layout diagrams of conventional examples, diagrams showing parasitic capacitance of signal wiring, circuit diagrams and equivalent circuit diagrams, and Figures 3 (a), (b) and (c). ) are layout diagrams, circuit diagrams, and equivalent circuit diagrams showing modifications of one embodiment, and FIG. 4(a),
(b) and (c) are cross-sectional views showing other modifications of one embodiment, a diagram showing parasitic capacitance of signal wiring, and an equivalent circuit diagram, and FIG. 5(a) is a ROM showing another embodiment of the present invention. The plan view of the chip, FIGS. 5(b) and 5(C), is a logic circuit diagram showing the chip enable buffer 550 and output enable buffer 560 of FIG. 5(a), respectively. 1,101,201... Semiconductor device, 2,10
2,202...Signal wiring, 103,203...
...Other signal wiring, 4,104,204...
・Drive circuit, 105, 205...Other drive circuits, 6, 106, 206, 7, 107, 207...
・Passive circuit, 108, 208... Semiconductor substrate,
109,209...Interlayer insulating film.

Claims (1)

[Claims] In a semiconductor device in which signal wiring for transmitting an output signal of a drive circuit to a passive circuit is provided on a semiconductor substrate, another drive circuit that generates a signal in phase with the drive circuit and an output signal of the other drive circuit are supplied. What is claimed is: 1. A semiconductor device comprising another signal wiring arranged parallel to the signal wiring.