JPS63116239A - Stack control system for processor - Google Patents

Abstract

PURPOSE:To prevent the generation of an abnormal operation or a runaway caused by the destruction of a data area other than a stack area or a program area by providing the titled system with a processor unit part and a stack unit part. CONSTITUTION:A stack area register part 111 in the stack unit part 11 stores an address in a stack area range set up by a microprocessor part 100 in the processor unit 10 and generates an interruption received by a maskable interruption control part 102. After receiving the interruption, stack operation is started and a stack area detecting part 112 compares a stack area access address based upon the stack operation with the range of a stack area in the register part 111 through a stack operation detecting part 110. At the time of accessing a stack area other than the range, a non-maskable interruption is instructed to the processor part 100 through a stack interruption part 113 or the like and the processor part 100 receiving the instruction displays a corresponding abnormal state and then processes restoring operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a computer system using a microprocessor, and more particularly to control of stack operations for memory during interrupts.

(Prior Art) Conventionally, destruction of areas outside the stack area due to this type of stack operation has been prevented by limiting the next interrupt during interrupt processing by operating interrupt mask control. That is, an attempt has been made to prevent destruction of areas outside the stack area by creating a program in consideration of the entire interrupt process so as not to exceed the usage of the stack area.

(Problems to be Solved by the Invention) In the conventional stack operation described above to prevent destruction outside the stack area, the stack area is secured in consideration of the entire normal four interrupt processing. Therefore, if abnormally frequent interrupts occur due to failures or interrupts occur with a frequency that exceeds the processing capacity, stack operations will overlap and exceed the stack area, causing other data areas and This has the disadvantage that it destroys the program, causing abnormal operation or runaway of the program, making it impossible to determine the cause of the abnormality and making it impossible to perform recovery processing.

An object of the present invention is to detect access from a processor to a memory section by stack operation.
The memory address range of the stack area is set by the processor, and when a memory access due to stack operation is detected, the address range of the stack area is checked, an access outside the range is detected, and a non-maskable interrupt is generated when an access outside the stack range is detected. The object of the present invention is to provide a stack control system for a processor that eliminates the above-mentioned drawbacks and prevents multiple stack operations from being performed simultaneously.

(Means for Solving the Problems) The processor stack control system according to the present invention is composed of a central processor unit section and a plurality of peripheral input/output I/IJ control unit sections, and the central processor unit section is connected to the processor unit section and the stack control system. This is a processor system composed of a unit section.

In the above configuration, the processor unit section includes a microprocessor section, a memory section, a maskable interrupt control section, a non-maskable interrupt control section, and an external interface section. Further, the stack unit section includes a stack operation detection section, a stack area register section, a stack area detection section, a stack interrupt section, and a stack control section.

In the above, when a large number of interrupts occur and access to the stack area due to stack operation exceeds the stack area range, non-maskable interrupts are notified to the microprocessor section, and the area outside the stack area is destroyed by performing a recovery operation. It is designed and constructed in such a way that it can prevent this.

The microprocessor section is for executing instructions, the memory section is for storing instructions and data, the maskable interrupt control section is for controlling maskable interrupts, and non-maskable interrupts. The control unit is for controlling non-maskable interrupts. The external interface section is for interfacing between the external peripheral input/output control unit section and internal hardware.

The stack operation detection section is for detecting that a stack operation from the microprocessor section to the memory section has been performed due to the occurrence of a maskable interrupt.

The stack area register section is for setting the address range of the memory section accessed in stack operation by the microprocessor section.

The stack area detection unit is for detecting an out-of-range address access from the address range fmK from the stack area register unit to the address to the memory section accessed by the stack operation when the stack operation detection unit detects the stack operation. be.

The stack interrupt section is for generating an interrupt outside the stack range in order to generate an interrupt to the horn maskable interrupt control section when the stack area detection section detects an out-of-range address access.

The stack control section is for executing control related to the entire stack out-of-range interrupt operation under control from the microprocessor section.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the processor stack control method according to the present invention. In FIG. 1, l denotes a central processor unit, 21.
22 are peripheral input/output control unit sections, 31 and 32, respectively.
are the peripheral parts, respectively. The central processor unit section 1 executes a program, and the peripheral input/output control unit sections 21 and 22 control the peripheral sections 31 and 32 according to instructions from the central processor unit section 1.

FIG. 2 is a block diagram showing one embodiment of the central processor unit l. Central processor unit part 1
Processor unit section 10. ! Niss stack unit part 1
The processor unit section 10 performs basic program execution control using a microprocessor and attached means, and the stack unit section 1] controls the stack operation of the processor unit section 1o.

FIG. 8 is a block diagram showing a detailed configuration example of the processor unit section.

In FIG. 8, a processor unit section 1o includes a microprocessor section 100.10 for executing instructions. ! :, a memory section 101 for storing instructions and data, and a peripheral control unit section 21.2 inside or outside the central processor section 1.
a maskable interrupt control unit 102 for controlling maskable interrupts from 2, a non-maskable interrupt control unit 103 for controlling forced interrupt-enabled nanomass pull interrupts inside the central processor unit 1, and an external peripheral input/output control unit. and an external interface section 104 for interfacing with the sections 21 and 22.

The microprocessor section 100 takes out the instructions stored in the memory section 101 and executes them one after another, thereby executing the program K. The maskable interrupt control section 102 processes a plurality of interrupts from the inside of the processor unit section 1 and the peripheral input/output control section units 21 and 22, and controls the control from the microprocessor section 100. It accepts an interrupt with a high value and causes the microprocessor unit 100 to generate an interrupt.

When the microprocessor section 100 receives an interrupt, it jumps to the corresponding interrupt processing. At the time of the jump and by saving registers by interrupt processing, the stack pointer in the stack area in the memory unit 101 (
Contains an address indicating the address to be used. ) The stack pointer is updated by sequentially performing a push process to store the instruction return address and registers in the stack area starting from the address indicated by . When the execution of the interrupt processing is completed, the register cover processing and the pop processing that read the registers and return address stored in the stack area by the return instruction are executed, and the execution returns to the state before the interrupt and the stack pointer is also restored. It is restored before the interrupt. During interrupt processing, when the next interrupt is accepted, the stack area is sequentially used in a similar manner.

The non-maskable control unit 103 is forcibly interrupted by the occurrence of the corresponding interrupt, and is accepted with priority over maskable interrupts.

Stack unit section] 1 is a microprocessor section 100
a stack operation detection unit 110 for accepting a maskable interrupt and detecting it by performing a stack operation to the memory unit 101; and a stack area for storing the stack area range of the memory unit 101 according to settings from the microprocessor unit 100. 11, the address to the memory unit 101 that was accessed during the stack operation when the stack operation detection unit 130 detected the stack operation, and the address of the stack area range stored in the stack area register unit 111, A stack area detection unit 112 for detecting an out-of-range access; and a non-maskable interrupt unit 113 for generating a stack area out-of-range access interrupt when the stack area detection unit 112 detects an out-of-range access; , and a stack control unit 114 for controlling the start/stop of operation for generating an out-of-stack area access interrupt based on instructions from the microprocessor unit 100.

The stack area register section 111 stores the address of the stack area range according to the settings from the microprocessor section 100, generates an interrupt that is accepted and processed by the maskable interrupt control section 102, and then generates an interrupt that is accepted and processed by the maskable interrupt control section 102.
When 0 accepts the corresponding interrupt, it starts stack operation. When an instruction is sent to the stack operation detection unit 112, the stack area detection unit 112 detects the stack area access address and stack area register 11 by the stack operation.
Compare the stack area range stored in 1.

When accessing outside the range of the stack area, the stack interrupt unit 1]3 is notified of the access outside the range.

The stack interrupt unit N13 interrupts the non-maskable interrupt control unit 10 when the stack control unit 114 is in the operation start state.
3. Generates an access interrupt outside the stack area range. In the corresponding interrupt, the non-maskable interrupt control unit 10
3, it instructs the microprocessor unit 300 to perform a mass pull interrupt.

The microprocessor unit 00 accepts a non-maskable interrupt that accesses outside the stack area, and after displaying the corresponding abnormal state, performs recovery operation processing.

(Effects of the Invention) As explained above, the present invention is capable of handling memory that exceeds the stack area due to abnormally high frequency of interrupts due to failures, interrupts with a high frequency of interrupts that exceed processing capacity, and stack operations that are deeper than expected. When an access is made, a non-maskable interrupt is generated to notify the processor of an access outside the stack area, thereby preventing abnormal operation or runaway due to destruction of the data area or program area outside the stack area, displaying the cause of the error, and recovering. It has the effect of enabling movement.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a processor system showing an embodiment of the processor stack control method according to the present invention. FIG. 2 is a block diagram showing an example of the configuration of the central processor section of FIG. 1. FIG. 8 is a block diagram showing a detailed configuration example of the processor unit shown in FIG. 11. 1.@Fist central processor unit section 21.22...
・Peripheral input/output control unit section 31, 32--Peripheral section 10--Processor unit section 110 Stack unit section 100...e Microprocessor section] 01-φ mesori section 102...Φ Maskable interrupt control Section 103...Non-maskable interrupt control section 104φ...
External interface section 110@...Stack operation detection section 111...Stack area register section 112...Stack area detection section 113-φ/Stack interrupt section 1]4...Stack control section

Claims (1)

[Claims] This is a stack control system for a processor system consisting of a central processor unit section and a plurality of peripheral input/output control unit sections, and the central processor unit section is composed of a processor unit section and a stack unit section. The unit section includes a microprocessor section for executing instructions, a memory section for storing instructions and data, a maskable interrupt control section for controlling maskable interrupts, and a non-maskable interrupt control section for controlling non-maskable interrupts. and an external interface section for interfacing between the peripheral input/output control unit section externally and the internal hardware, and the stack unit section a stack operation detection section for detecting that a stack operation has been performed from the processor section to the memory section; and a stack area register for setting the address range of the memory section accessed by the stack operation from the microprocessor section. and a stack area for detecting an out-of-range address access by using an address range from the stack area register section to detect an address to the memory section accessed by the stack operation when the stack operation detecting section detects a stack operation. a detection section; a stack interrupt section for generating an interrupt outside the stack range; and the microprocessor section for generating an interrupt to the non-maskable interrupt control section when the stack area detection section detects the out-of-range address access; and a stack control unit for executing overall control of interrupt operations outside the stack range under control from the stack control unit, and when a large number of interrupts occur and access to the stack area by the stack operation exceeds the range of the stack area. ,
1. A processor stack control system, characterized in that the microprocessor section is notified by the non-maskable interrupt and a recovery operation is performed to prevent destruction outside the stack area.