JPH06259288A - Runaway monitor circuit for cpu - Google Patents

Abstract

PURPOSE:To speedily perform runaway detection by previously storing the next address corresponding to the program of the instruction of a CPU and always comparing this next address with the next program address generated by the CPU. CONSTITUTION:While a CPU 1 executes the instruction, the present program address is imparted from the CPU 1 to a next address storage memory 21 so that the next program address can be read from the memory 21 and latched by a next address storage register 22. At the time point when the CPU 1 generates the program address of the next instruction, the address latched by the next address storage register 22 is inputted to a comparator 3 so that the comparator 3 can compare the next program addresses each other. As a result, when non-coincidence occurs, a runaway detecting signal (c) showing the start of runaway of the CPU 1 is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway monitoring circuit for a microprocessor (hereinafter referred to as CPU), and more particularly to a CPU.
The present invention relates to a runaway monitoring circuit of a signal processing circuit using the.

In recent years, signal processing circuits using CPUs have been applied to devices in all fields.
May run out of control for some reason, and the influence of such a fault condition on the signal processing circuit is immeasurable. Therefore, a runaway monitoring circuit capable of rapid detection is required.

[0003]

2. Description of the Related Art Conventionally, a watchdog timer, a bus parity monitoring circuit, an invalid address access monitoring circuit, etc. have been known as CPU runaway monitoring circuits.

Of these, the watchdog timer is CP
A certain time interrupt is given to U, and the CPU responds to this to periodically access the register. This periodic access is monitored on the hardware, and this can be confirmed. If there is not, it is determined that the CPU is out of control.

The bus parity monitoring circuit monitors the runaway state by adding a parity bit to the bus itself of the CPU and determining whether or not the parity at each point is normal.

Further, in the invalid address access monitoring circuit, the memory and peripheral input / output circuits (I / I)
Since a fixed address is assigned to (O),
It is determined that the CPU is out of control when an impossible address other than those is accessed.

[0007]

Since the watchdog timer described above is periodically accessed, CPU runaway cannot be detected in the middle of the access interval, and it takes time to detect runaway.

Further, in the case of the bus parity monitoring circuit,
Since the normality / abnormality of the bus is monitored instead of monitoring the CPU itself, the parity becomes normal even during a runaway, and a reliable runaway cannot be detected.

Further, the invalid address access monitoring circuit does not monitor the CPU itself,
Since the addresses for memory and peripheral I / O are monitored, when the CPU does not run out of control, it is considered to be in a runaway state when the invalid address is accessed. May be determined to be normal by accessing.

As described above, in the conventional technique, there are problems that it takes time to detect a runaway and reliable monitoring cannot be performed.

As a result, at the time of the runaway detection, the data in the register and the memory have already been destroyed, and it is almost impossible to restore the state before the runaway.

Therefore, the present invention realizes quick and reliable runaway monitoring, and can restore the state before runaway to a CP.
It is intended to provide a runaway monitoring circuit for U.

[0013]

In order to achieve the above object, the runaway monitoring circuit of the CPU according to the present invention, as shown in principle in FIG. 1, sets the following address to the program address of the instruction of the CPU1. The next address storage unit 2 stored in advance, the address of the next address storage unit 2 and the CPU 1
And a comparator 3 which always compares the next program address generated by the above-mentioned (1) and generates a runaway detection signal of the CPU 1 when these do not match.

Further, according to the present invention, as shown by a dotted line in FIG. 1, a current address storage unit 4 for constantly storing the current address of the program address is provided, and when the runaway detection signal is given to the CPU 1 as a reset signal. It is possible to return the operation of the CPU 1 to the current address of the current address storage unit 4.

[0015]

The operation of the runaway monitoring circuit of the CPU according to the present invention shown in FIG. 1 will be described with reference to FIG.
When 1 is executing an instruction at a certain address, the program address of the next instruction after processing that instruction is C
According to the program of PU1, it is divided as follows as shown in FIG. a) Simple process: After the process is completed, the address is incremented by 1, and the process proceeds to the next address. b) Conditional jump X: If the condition is satisfied, the condition is jumped to the address X, and if not satisfied, the address is incremented by 1 and the process proceeds to the next address. c) Unconditional jump X: Unconditionally jump to address X.

Here, since the address of the program to be accessed next by the CPU 1 is stored in advance in the next address storage unit 2 in correspondence with the content of the program which the CPU 1 actually operates, the CPU 1 issues an instruction. When the program address of the next instruction is executed and the next instruction is generated, the expected value (address) is extracted from the next address storage unit 2 and these are compared by the comparator 3.

For example, the current program address is "03".
When the program content is a simple process, the next program address is "04". Therefore, if the CPU 1 is operating normally, the current program address "0"
4 ”matches the address“ 04 ”stored in the next address storage unit 2. This is performed in the same manner even if the program content is "conditional jump" or "unconditional jump" because the jump destination address or the simple processing address is specified.

On the other hand, if a mismatch occurs as a result of the address comparison, it can be detected at this point that the runaway of the CPU 1 has started.

Further, according to the present invention, if the current program address is constantly stored in the current address storage section 4 shown by the dotted line, the CPU 1 will operate at the time when the above-mentioned runaway detection signal from the comparator 3 is sent to the CPU 1. The operation can be restarted from the current address of the current address storage unit 4, that is, the instruction immediately before the runaway, and the influence of the disturbance due to the runaway can be reduced.

[0020]

FIG. 3 shows an embodiment (part 1) of a runaway monitoring circuit for a CPU according to the present invention. In this embodiment, in addition to the CPU 1 and the program memory 5 which are the constituent elements of a normal CPU circuit. The next address storage memory 21 for storing the address of the next instruction, the next address storage register 22 for extracting the expected value from the memory 21, and the comparator 3 for comparing the expected value with the address generated by the CPU 1. The memory 21 and the register 22 constitute the next address storage unit 2.

In the operation of this embodiment, as described above, the current program address when the CPU 1 is executing an instruction is given from the CPU 1 to the next address storage memory 21, so that the memory 21 is shown in FIG. The next program address is read out, given to the next address storage register 22 and latched.

Then, when the CPU 1 generates the program address of the next instruction, the next address storage register 2
Since the next program address latched by 2 is supplied to the comparator 3, the comparator 3 compares the next program addresses with each other.

As a result, if a mismatch occurs, the CP
A runaway detection signal indicating that the runaway of U1 has started is generated.

FIG. 4 shows a configuration of an embodiment (part 2) of the present invention for restoring the state before the runaway by applying the runaway monitoring circuit of FIG. 3, and in this embodiment, FIG. In addition to the runaway monitoring circuit of FIG. 1, a current address storage register 4 is provided as a current address storage unit for storing the current address at which the instruction is being executed, and the address stored in this register 4 is always used by the CPU 1 in the program memory 5. Of the reset vector 50.

Therefore, when the runaway of the CPU 1 is detected by the next address storage unit 2 and the comparator 3, the comparator 3 causes the CPU
1 is reset by applying a reset signal to the reset terminal RST of the CPU 1.

At this point, the reset vector 50 of the CPU 1
Indicates the program address immediately before the runaway, so C
PU1 can be restarted from the instruction immediately before the occurrence of the runaway, and the influence of the disturbance due to the runaway can be reduced.

[0027]

As described above, the CP according to the present invention
According to the runaway monitoring circuit of U, the next address is stored in advance with respect to the program address of the instruction of the CPU, and this next address and the next program address generated by the CPU are constantly compared with each other to cause a mismatch. CPU when
Of the program address, the current address of the program address is constantly stored, and when the runaway detection signal is given to the CPU as a reset signal, the CPU is restored to the current address. Since each address is constantly monitored, rapid runaway detection can be performed without error, and at the time of runaway, the operation can be restored from the instruction immediately before the runaway and data protection can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing in principle a runaway monitoring circuit of a CPU according to the present invention.

FIG. 2 is an operation explanatory diagram of the runaway monitoring circuit of the CPU according to the present invention.

FIG. 3 is a block diagram showing an embodiment (No. 1) of the runaway monitoring circuit of the CPU according to the present invention.

FIG. 4 is a block diagram showing an embodiment (No. 2) of the runaway monitoring circuit of the CPU according to the present invention.

[Explanation of symbols]

 1 CPU Secondary address storage unit 3 Comparator 4 Current address storage unit In the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (2)

[Claims] 1. A next address storage unit (2) for pre-storing the next address for a program address of an instruction of the CPU (1), and an address of the next address storage unit (2) and the CPU (1) A CPU runaway characterized by comprising a comparator (3) for constantly comparing the generated next program address and generating a runaway detection signal of the CPU (1) when these do not match. Monitoring circuit. 2. A current address storage unit (4) for constantly storing the current address of the program address is provided, and when the runaway detection signal is given to the CPU (1) as a reset signal, the CPU (1) is activated. The C according to claim 1, wherein the operation is returned to the current address of the current address storage unit (4).
PU runaway monitoring circuit.