JPH1063541A - Program hang-up monitor device for computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a program runaway without applying any heavy load to a CPU by comparing the address specified with the output value of a program counter with a stored branch destination address in response to a branch detection signal. SOLUTION: The output value of an address incrementor 21 is equal to the count value of a program counter 11a unless a CPU 11 jumps an execution address. A branch detecting circuit 22 compares the output value of the address incrementor 21 with the address data value of an address bus 12 and generates a branch detection signal unless they match each other. A branch destination address comparing circuit 23 compares the branch destination address from a branch memory 15 that a branch register 20 holds with the address that address data supplied from the address bus 12 indicates. When the comparison result of the branch destination address comparing circuit 23 indicates a discrepancy, a hang-up detection signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a program runaway monitoring device in a computer system.

[0002]

2. Description of the Related Art In computer systems, CP
The operation of the U (central processing unit) may deviate from a normal operation in accordance with the execution order of the program due to the influence of disturbance noise or the like, causing a so-called program runaway. In order to monitor this program runaway, a specific process is executed by the CPU at regular intervals during the actual program processing, and the normal operation of the computer has been confirmed from the execution result of the specific process. .

[0003]

However, in such a conventional program runaway monitoring, if a certain period of time, which is an interval for executing such a specific process, is set to be long, the load imposed on the CPU by the specific process is reduced. Although less is required, when the CPU goes out of control, the malfunctioning period from the occurrence of the program runaway to the detection of the program becomes longer. The adverse effects on the computer system are enormous. On the other hand, if the fixed time is set short, the malfunction period is shortened, but there is a problem that the load imposed on the CPU by the specific processing increases.

An object of the present invention is to provide a program runaway monitoring device for a computer system which can appropriately detect program runaway without causing a large load on the CPU.

[0005]

According to the present invention, there is provided a program runaway monitoring apparatus for a computer system, wherein a storage location of a program memory storing a program including a plurality of instructions including at least one branch instruction is determined by an output value of a program counter. A program runaway monitoring device for a computer system, which designates an address and reads and executes a program instruction stored in a storage location of the specified program memory, wherein an instruction to be executed immediately after branching by a program branch instruction Branch destination storage means for storing a branch destination address indicating the storage location of the program memory in which is stored, and branch detection means for generating a branch detection signal by detecting that the output value of the program counter has changed discontinuously, Change the output value of the program counter in response to the branch detection signal As a comparison result by comparing the stored branch destination address to the address and the branch destination storage unit specified is characterized in that a comparison means for generating a runaway detection signal if a mismatch I.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 schematically shows a computer system provided with a program runaway monitoring device according to the present invention. In this computer system, C
An address bus 12 extending from an output of a built-in program counter (PC) 11a of a PU (central processing unit) 11 has a RAM (random access memory) 13, a ROM (read only memory) 14, a branch destination memory 15, and a runaway monitoring circuit. 16 are connected. A RAM 13 and a ROM 14 are connected to a data bus 17 extending from a CPU (Central Processing Unit) 11.

A program to be executed by the CPU 11 is stored in the ROM 14 in advance. The CPU 11 reads an instruction from an address of the ROM 14 designated by a value of a built-in program counter 11a and executes the instruction. The branch destination memory 15 is composed of, for example, a read-only memory,
There are 14 storage locations corresponding to each address. That is, the same address as the ROM 14 is assigned to the branch destination memory 15. Further, the branch destination memory 15 stores in advance only the branch destination addresses of the branch instructions such as the forced jump instruction and the conditional jump instruction in the program stored in the ROM 14. The storage location of the branch destination memory 15 from the first address in the program to the address of the first branch instruction stores the branch destination address of the first branch instruction. The branch destination address of the next branch instruction is stored in the storage location of the branch destination memory 15 from the address following the address of one branch instruction to the address of the next branch instruction in the program. The branch destination memory 15 outputs the branch destination address stored at the address indicated by the address data supplied from the address bus 12 as a data value.

Note that a RAM can be used as the branch destination memory 15. In such a case, the necessary branch destination address may be written into the RAM when the system is started. As shown in FIG. 2, runaway monitor circuit 16 includes branch destination register 20, address incrementer 21 connected to address bus 12, and branch detection circuit 2.
2 and a branch destination address comparison circuit 23. The branch destination register 20 holds the branch destination address read from the branch destination memory 15. This branch destination address is held and output until the next instruction is set in the CPU 11 (or in the case of a branch, the branch destination address is output from the program counter 11a of the CPU 11).
The address incrementer 21 is composed of a programmable counter, inputs address data from the address bus 12 in accordance with the contents of the operation information signal supplied from the CPU 11, sets it as an initial count value, and counts up one by one at a clock pulse generation timing. I do. Therefore, the output value of the address incrementer 21 is the same as the count value of the program counter 11a unless the CPU 11 jumps the execution address with a branch instruction. The branch detection circuit 22 is connected to the output of the address incrementer 21, compares the output value of the address incrementer 21 with the address data value of the address bus 12, and generates a branch detection signal when the comparison result does not match. Branch destination address comparison circuit 23
Is connected to the output of the branch detection circuit 22, and the branch detection circuit 2
2 supplies a branch detection signal. Further, the branch destination address comparison circuit 23
When the branch detection signal is supplied from the branch register 20, the branch destination address held and output by the branch register 20 is compared with the address indicated by the address data supplied from the address bus 12. The comparison result of the branch destination address comparison circuit 23 is output to the CPU 11 as a runaway monitoring output signal.

FIG. 3 partially shows program instructions stored in the ROM 14 in the order of addresses. Here, the general instruction is an instruction that does not involve branching, and is, for example, an operation instruction, a data movement instruction, and a control instruction. A branch instruction is an instruction having a branch destination address, such as a forced jump instruction that branches unconditionally or a conditional jump instruction that branches if a predetermined condition is satisfied and does not branch if the condition is not satisfied. A branch destination address is added to each branch instruction as (@AA). Note that "@" indicates that the value following it is an address, and for clarity, it is a two-digit hexadecimal address.

FIG. 4 partially shows the storage contents of the branch destination memory 15 corresponding to the program shown in FIG. 3 in the order of addresses. That is, as can be seen from the program of FIG. 3, the branch instruction ($ A
A) is stored, the address $ A is stored in each storage location from the address $ 00 to the address $ 04 of the branch destination memory 15.
A is stored. In the ROM 14, the address $ 0
4, the branch instruction exists at address $ 1A. Since the branch instruction ($ BB) is stored at address $ 1A, addresses $ 05 to $ 5 of branch destination memory 15 are stored.
An address $ BB is stored in each storage location of $ 1A. Similarly, in the ROM 14, the branch instruction next to the address $ 1A exists at the address $ 23. Since the branch instruction ($ CC) is stored in the address $ 23A, the address of the branch destination memory 15 is stored. $ 1B to $ 2
The address $ CC is stored in each storage location of No. 3.
As described above, the branch destination address of the next branch instruction is stored in each storage location of the branch destination memory 15 from the address next to the address of one branch instruction in the program to the address of the next branch instruction.

Next, the operation of runaway monitor circuit 16 when CPU 11 operates according to the program shown in FIG. 3 will be described. The CPU 11 determines the address of the program.
When execution is started from the instruction of 00, addresses are sequentially specified from address $ 00 by a counting operation synchronized with a clock pulse by the program counter 11a of the CPU 11. Address data indicating the designated address is supplied to the ROM 14 and the branch destination memory 15 via the address bus 12. The instruction at the storage location of the designated address is read from the ROM 14 and
The instruction is supplied to the PU 11, and the CPU 11 decodes and executes the instruction every time the instruction is supplied from the ROM 14. If the instruction is a branch instruction, it is determined whether or not to branch to a branch destination address according to the execution result. If the branch is not taken, the value of the program counter 11a is counted up in response to the next clock pulse. When branching, the branch destination address is set in the program counter 11a, and address data indicating the branch destination address is supplied to the ROM 14 and the branch destination memory 15 via the address bus 12. The instruction at the storage location of the branch destination address is read from the ROM 14 and supplied to the CPU 11 via the data bus 17, and the CPU 11 decodes and executes the instruction, thereby repeating the above operation.

When the address data is supplied to the ROM 14 and the branch destination memory 15 via the address bus 12, the instruction is read from the ROM 14 as described above,
In the branch destination memory 15, the branch destination address stored in the storage location specified by the address data is read and held in the branch register 20. The branch destination address held in the branch register 20 is immediately output to the branch destination address comparison circuit 23 when the output value of the program counter 11a is $ 00, but thereafter the next instruction is installed in the CPU 11 as described above. And is supplied to the branch destination address comparison circuit 23.

In the address incrementer 21,
After the address data, which is the value of the program counter 11a, is input from the address bus 12 according to the contents of the operation information signal supplied from the CPU 11, the address data value is used as an initial value to count up in synchronization with a clock pulse ( As a result, the same value as the count value of the program counter 11a is output to the branch detection circuit 22 unless the branch destination address is set in the program counter 11a. Therefore,
As long as the branch destination address is not set in the program counter 11a, the branch detection circuit 22 does not generate a branch detection signal because the output value of the address incrementer 21 matches the address data value from the address bus 12.

When the branch destination address is set in the program counter 11a because the branch operation has been performed as described above, the CPU 11 sends the address incrementer 2
The content of the operation information signal supplied to 1 does not change immediately,
Since the output value of the address incrementer 21 is simply a value counted up, the output value of the address incrementer 21 does not match the address data value from the address bus 12. Thereby, the branch detection circuit 22 generates a branch detection signal.

The branch detection signal is transmitted to the branch destination address comparison circuit 2
3, the branch destination address comparison circuit 23 compares the branch destination address output from the branch register 20 with the current address indicated by the address data supplied from the address bus 12 in response to the branch detection signal. I do. If the branch destination address matches the current address, the actual branch destination address indicated by the program counter 11a matches the predetermined branch destination address, indicating that the branch operation has been performed correctly. Therefore, the branch destination address comparison circuit 23 outputs a runaway monitoring output signal indicating normal.

On the other hand, when the output value of the program counter 11a changes due to program runaway without performing a normal count-up operation, the output value of the address incrementer 21 and the address bus 12 are changed in the same manner as in the branch operation described above. The branch detection circuit 22 generates a branch detection signal because the address data value no longer matches the address data. However, since the output value of the program counter 11a changed by the program runaway usually does not coincide with the branch destination address output from the branch register 20, the branch destination address comparison circuit 23 outputs a runaway monitoring output signal indicating an abnormality. Output as runaway detection signal. The runaway monitoring output signal indicating this abnormality is supplied to the CPU 11 as a reset signal, and the operation of the CPU 11 is initialized.

FIG. 5 shows the progress of the instruction by the execution of the program shown in FIG. 3, and changes in the address specified by the program counter 11a and the address output from the branch register 20. Here, as indicated by a double line, the progress of the instruction corresponds to the branch instruction at addresses $ 04 and $ 1A in the program shown in FIG.
11 executes the instruction at the next address without branching,
It is assumed that the branch instruction at address $ 23 is branched and the instruction at branch destination address $ CC is executed.

That is, the address $ 04 in the program
Is executed, and the branch instruction ($ AA) is executed.
, The instruction at the next address $ 05 is executed without branching. Until the address $ 05 is executed, the address output from the branch register 20 is $ AA.
When the address $ 06 following the address $ 05 is designated,
The address output from branch register 20 is $ BB. Thereafter, the branch instruction ($ BB) at address # 1A is executed, and the address output from branch register 20 is $ BB until address # 1B is further executed. The instruction at the next address # 1B is executed without branching from the execution of the branch instruction ($ BB). And address $ 1
When the address $ 1C next to B is specified, the address output from the branch register 20 becomes $ CC. afterwards,
The branch instruction ($ CC) at address # 23 is executed, and the branch is executed by execution of the branch instruction ($ CC). When the program counter 11a is set at the branch destination address $ CC, a branch detection signal is generated. By the generation of the branch detection signal, the comparison operation of the branch destination address comparison circuit 23 is performed. Since both the address output from the branch register 20 and the current address match at $ CC, it is determined from the output signal of the branch destination address comparison circuit 23 that it is normal.

If the address indicated by the program counter 11a moves from $ 20 to $ EF due to program runaway as shown by an arrow in the program execution progress state of FIG. 5, a branch detection signal is generated. , The comparison operation of the branch destination address comparison circuit 23 is performed. However, since the output address held in the branch register 20 at this time is $ CC, it does not match the current address $ EF. Therefore, the output signal of the branch destination address comparison circuit 23 is determined to be abnormal.

In the above-described embodiment, the address data is taken in from the address bus 12 by the address incrementer 21 based on the contents of the operation information signal from the CPU 11, but is output from the branch detection circuit 22. This may be performed in response to a branch detection signal. In addition, the address incrementer 21 stops counting when the CPU 11 is reading data from the RAM 13, when changing the address due to an interrupt, or when returning to normal processing from interrupt processing or subroutine processing. The counting up is stopped in response to the operation information signal. Further, when the counting up is stopped, the comparison operation of the branch destination address comparison circuit 23 is also stopped according to the operation information signal.

In the above embodiment, when a runaway monitoring output signal indicating an abnormality is output, the CPU 11
Only the reset is performed. However, the present invention is not limited to this. The entire system may be reset, or the process may be returned to the program process after performing a predetermined runaway detection process without resetting. Further, the operation state of the system may be reset, for example, by recording the operation state of the system in a printer output or an external memory in order to analyze the abnormal part. Further, in the case of a multiple computer system, it is also possible to exclude a result such as data output from a system in which an abnormality is detected from a material for determination in subsequent processing.

Further, in the above-described embodiment, the runaway monitoring circuit 16 has a power supply 19 and a ground separated from the power supply 18 and the ground of the CPU 11, respectively. This is to prevent the same power supply or ground abnormality from affecting both the CPU 11 and the runaway monitoring circuit 16 at the same time. In the above-described embodiment, the branch destination memory 15 has storage locations corresponding to all the addresses of the ROM 14, and the branch destination address is stored in each storage location. Until the address at which the instruction is located is executed, the same branch destination address can be easily read from one storage location of the branch destination memory 15 by using, for example, a logic circuit. Thus, the branch destination memory 1
By storing and storing only the necessary number of branch destination addresses at 5, the storage capacity of the branch destination memory 15 can be small.

The branch detection circuit 22 in the above embodiment compares the output value of the address incrementer 21 with the address data value supplied to the address bus 12, but is supplied to the address bus 12. A branch detection signal may be generated only when it is detected that the address data value has changed discontinuously. The output value of the program counter 11a changes continuously when only the general instruction in the program is executed, and the case where such a continuous change does not occur is discontinuous. Further, in the embodiment, the output value of the program counter 11a is shown to change by one. However, the present invention is not limited to this, and may change by a predetermined value, for example, by two.

Further, the program runaway monitoring device of the present invention may be combined with a conventional runaway detection method in which the CPU performs a specific process of the program runaway at regular time intervals. With such a combination, runaway detection accuracy can be improved. For example, as shown in FIG.
Assuming that a subroutine for writing / erasing an EEPROM (programmable ROM capable of electrically erasing) is located in the address assigned to M, in the example shown by the symbol A, a runaway that does not branch from normal operation occurs and at least This is a case where the execution position reaches the subroutine after a lapse of a predetermined time or more, and the subroutine is executed and the data in the EEPROM is destroyed. In the example indicated by reference character B, runaway due to branching from normal operation occurs, the execution position immediately reaches a subroutine, and the subroutine is executed to destroy data in the EEPROM. In the case of Example A, a conventional runaway detection method in which a specific process is performed at regular intervals is considered to be effective. On the other hand, in the case of Example B, it is difficult to detect runaway with the conventional runaway detection method, and it is considered effective to use the program runaway monitoring device of the present invention. Therefore, if the program runaway monitoring device of the present invention is provided in combination with the conventional runaway detection method, both cases A and B described above can be dealt with.

[0025]

As described above, according to the present invention,
A branch destination memory is provided which stores a branch destination address indicating a storage location of a program memory in which an instruction to be executed is stored immediately after branching by a branch instruction of a program, and that the output value of the program counter changes discontinuously. When detected, the CPU compares the address specified by the output value of the program counter with the branch destination address stored in the branch destination memory, and generates a runaway detection signal if the comparison result does not match. Therefore, it is possible to appropriately detect program runaway without executing a specific process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a computer system to which a program runaway monitoring device according to the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of a runaway monitoring circuit.

FIG. 3 is a diagram showing an instruction for each address in a ROM.

FIG. 4 is a diagram showing a branch destination address for each address of a branch destination memory;

FIG. 5 is an example showing the progress of an instruction to explain the operation of the device of FIG. 1;

FIG. 6 is an address space diagram for showing two different runaway examples.

[Description of Signs of Main Parts]

 Reference Signs List 11 CPU 11a Program counter 12 Address bus 13 RAM 14 ROM 15 Branch destination memory 16 Runaway monitor circuit 17 Data bus 20 Branch destination register 21 Address incrementer 22 Branch detection circuit 23 Branch destination address comparison circuit

Claims (3)

[Claims] An address of a storage location of a program memory in which a program including a plurality of instructions including at least one branch instruction is stored is designated by an output value of a program counter, and stored at the designated storage location of the program memory. A program runaway monitoring device for a computer system that reads and executes an instruction of a program that has been executed, wherein a branch destination address indicating a storage location of a program memory in which an instruction to be executed is stored immediately after branching by a branch instruction of the program. Stored branch destination storage means; branch detection means for detecting that the output value of the program counter has changed discontinuously to generate a branch detection signal; output value of the program counter in response to the branch detection signal Stored in the branch destination storage means and the address specified by A program runaway comparing device for comparing the program with a branch destination address and generating a runaway detection signal if the comparison result indicates a mismatch. 2. An address incrementer for counting up from an initial value of the program counter in synchronization with a clock pulse and outputting the count value, and an output value of the program counter and an address incrementer. 2. The program runaway monitoring device according to claim 1, further comprising: a branch detection circuit for generating a branch detection signal when the count value does not match. 3. The same address group as that of the program memory is allocated to the branch destination storage means, and the branch destination storage means corresponds to each address in the order of addresses up to the address of the storage position where the branch instruction is stored in the program memory. 2. The program runaway monitoring device according to claim 1, wherein a branch destination address of the branch instruction is stored in each storage location of the branch destination storage means.