JPH08235026A - Cpu operation abnormality detection system - Google Patents

Abstract

PURPOSE: To provide a CPU operation abnormality detection system which can shorten the time needed for detection of such abnormality as the runaway of a CPU, etc. CONSTITUTION: The access inhibition information is generated by the execution of an initialization program that is stored in a ROM of a ROM/RAM/input- output control circuit part 20 and then written in a monitoring point memory part 1 by a memory control circuit part 2. Then the part 2 reads the access inhibition information corresponding to an execution address out of the part 1 and inputs the inhibition information to a CPU control circuit part 11 via a synthesization circuit 3.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CPU (central processing unit).
More particularly, the present invention relates to a CPU operation abnormality detection system that detects an abnormal operation state under software control such as CPU runaway.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional CPU operation abnormality detection system. A conventional CPU operation abnormality detection system includes a CPU control circuit unit 11 for executing and controlling program instructions, and an R for storing a program instruction group indicating processing contents.
An OM unit 12, a RAM unit 13 for storing and storing a data group of a processing process and a processing result, a timer control circuit unit 14 for monitoring a normal operation of CPU control by counting a processing time at a constant interval, and an external unit. It has an input / output control unit 15 for controlling the information input / output and a memory / parity generation / inspection circuit unit 16 for generating and inspecting a parity bit when reading / writing the memory.

In this CPU operation abnormality detection system, in order to detect an abnormal operation state due to software control such as CPU runaway due to error access to a data area, stack area overflow, etc. in addition to abnormal operation of hardware, timer control is performed. The circuit section 14 measures the processing time of a fixed cycle by a counter (for example, a watch dog timer) or the like, and detects an abnormal operation state when the timer is over.

As a prior art for detecting CPU runaway, (1) Japanese Patent Laid-Open No. 60-183641 discloses a runaway detection output when an address outside the stack area in RAM and in the immediate vicinity of the stack area is detected. A system for detecting runaway of a CPU having a generated address recorder is disclosed. (2) Japanese Patent Laid-Open No. 61-279940
By detecting that the contents of the CPU stack pointer or program counter have become equal to the limit value of the RAM stack area or data area, the stack area or data area overflow is detected, and software runaway is detected. An abnormality detecting device for a computer is disclosed. (3) Japanese Patent Laid-Open No. 61-279941 discloses a stack area by detecting that a CPU has written data in the deepest memory address of the RAM stack area. Of the above, a computer abnormality detection device for detecting overflow of software and detection of software runaway is disclosed.

[0005]

However, the conventional CPU
Since the operation abnormality detection system measures the processing time of a fixed cycle with a counter or the like, the elapsed time from the occurrence of the abnormal operation to the abnormality detection / countermeasure processing was very long.

Further, the prior arts (1) to (3) do not disclose the technology for storing the access-prohibited address information in the memory.

Therefore, an object of the present invention is to provide a CPU operation abnormality detection system capable of shortening the time required for abnormality detection such as CPU runaway.

[0008]

In order to solve the above-mentioned problems, the present invention relates to a storage means for storing access prohibition information indicating an access-prohibited address for a memory address defined during CPU operation, and a memory means during the CPU operation. Storage control means for reading out the access prohibition information corresponding to the always-executed address from the storage means.

[0009]

Since the access prohibition information corresponding to the always-executed address is read from the storage means, it is immediately known whether the execution address is the access-prohibited address.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an embodiment of a CPU operation abnormality detection system according to the present invention. In the figure, the same components as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

The CPU operation abnormality detection system includes a CPU control circuit section 11 for executing and controlling a program instruction, a ROM section / RAM section for storing data such as a program instruction group showing program processing contents and a process, and the outside. ROM / RAM / consisting of I / O unit for controlling information input / output
A parity bit generation / parity bit generation / monitoring by the input / output control circuit unit 20, a counter (for example, a watchdog timer) that periodically measures the processing time for confirming the normality of the CPU control, and a ROM / RAM unit by a parity bit generation / inspection An operation monitoring circuit unit 21 including a check circuit, a ROM unit,
The access prohibition information indicating the access prohibition address is stored in the RAM unit and the I / O unit, the access prohibition information corresponding to the constantly executed address is read in the CPU operating state, and the access prohibition information is output as the CPU monitoring result. Point memory unit 1 and a memory control circuit for writing access prohibition information to the monitoring point memory unit 1 by CPU control processing (for example, initialization processing) based on monitoring contents defined according to various CPU systems at the start of operation. 2 and a synthesis circuit 3 that synthesizes the access prohibition information output from the monitoring point memory unit 1 and the monitoring result information output from the operation monitoring circuit unit 21 and outputs the synthesized result to the CPU control circuit unit 11. .

The operation monitoring circuit section 21 is an operation monitoring circuit similar to the conventional one, and the monitoring result is C through the combining circuit 3.
It is output to the PU control circuit unit 11.

On the other hand, the monitoring point memory unit 1, the memory control circuit 2 and the synthesis circuit 3 are new. Next, operations of the monitoring point memory unit 1, the memory control circuit 2 and the synthesizing circuit 3 will be described.

FIG. 2 is a schematic explanatory view showing the operation of the CPU operation abnormality detection system. In the figure, the program RO
M and the work RAM correspond to the ROM / RAM / input / output control circuit unit 20 (hence the same reference numerals), 1
The bit memory corresponds to the monitoring point memory unit 1 (hence the same number). As described above, in this embodiment, the 1-bit memory (RAM or ROM) is used as the monitoring point memory unit 1.

Now, as an example, a program ROM and a work RAM that are accessed (including an I / O area)
Memory area of the program area A as shown in FIG.
(Usable), empty area B (unusable), program area C
(Usable), empty area D (unusable), work area E
It is allocated to (usable), empty area F (unusable), and initialization program area G (usable).

"1" is stored in the 1-bit memory 1 in association with usable memory addresses A, C, E, G, and "0" in correspondence with the unusable addresses B, D, F. Is remembered.

In this state, when the CPU operation is started, the access prohibition information corresponding to the always-executed address, that is, the content of the 1-bit memory (monitoring point memory section) 1 is read out, and the content of the 1-bit memory 1 is changed. It is input to the CPU control circuit unit 11 via the synthesis circuit 3. The memory control unit 2 controls the reading of the access prohibition information from the 1-bit memory 1.

Therefore, it is possible to immediately detect whether or not the accessed address can be used for each execution address during CPU operation.

When only a certain CPU system is executed, it is sufficient to previously write certain access prohibition information in this 1-bit memory. Therefore, in this case, the ROM can be used as the 1-bit memory.

Next, a description will be given of an abnormality detection system in which not only a fixed CPU system but also various CPU systems are executed. "Writing the access prohibition information to the storage means based on the monitoring contents defined according to various CPU control systems" means that the use of the memory address of the ROM part, the RAM part, or the input / output control circuit part is clear. And write the access prohibition information to the storage means for the memory address that is not used. "

In this case, the access prohibition information is generated by executing the initialization program stored in the ROM of the ROM / RAM / input / output control circuit section 20, and the memory control circuit section 2 stores this information in the 1-bit memory. Write to 1.

Therefore, access prohibition information corresponding to various initialization programs can be written in the 1-bit memory 1. In this case, it is necessary to use a rewritable memory such as a RAM as the 1-bit memory.

The reading of the access prohibition information corresponding to the execution address is the same as in the case where only the certain CPU system described above is executed, and the description thereof will be omitted.

Next, the access prohibition information is read from the 1-bit memory 1, and this access prohibition information is synthesized.
When input to the CPU control circuit unit 11 via
The control circuit unit 11 performs abnormality countermeasure control according to various CPU systems, for example, control such as operation stop at abnormality, HALT processing, or restart after execution of initialization processing.

Although a 1-bit memory is used as the monitoring point memory unit, it is not limited to 1 bit, and for example, 2 bits "11" indicates that the use is possible and "00" indicates that the use is not possible. Good.

Unusable area (access prohibited area)
Can be set at any point in addition to the boundaries of various programs.

[0027]

According to the present invention, storage means for storing access prohibition information indicating an access prohibition address for a memory address defined during CPU operation and access prohibition information corresponding to a constantly executed address during CPU operation are provided. Since the CPU operation abnormality detection system is configured to include the storage control unit that reads from the storage unit, it is possible to immediately determine whether the execution address is the access-prohibited address.

Further, since the access prohibition information is written in the storage means based on the monitoring contents defined according to various CPU control systems at the time of starting the CPU operation, the CPU operation abnormality detection system corresponding to various system software is constructed. can do.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a CPU operation abnormality detection system according to the present invention.

FIG. 2 is a schematic explanatory view showing an operation of the CPU operation abnormality detection system.

FIG. 3 is a configuration diagram of a conventional CPU operation abnormality detection system.

[Explanation of symbols]

 1 monitoring point memory unit 2 memory control circuit 11 CPU control circuit unit 20 ROM / RAM / input / output control circuit unit

Claims (3)

[Claims] 1. A storage unit for storing access prohibition information indicating an access prohibition address for a memory address defined during CPU operation, and the access prohibition information corresponding to an always-executed address during the CPU operation from the storage unit. A CPU operation abnormality detection system comprising a storage control unit for reading. 2. The storage control means includes means for writing the access prohibition information in the storage means based on monitoring contents defined according to various CPU control systems at the time of starting the CPU operation. CP of 1
U operation abnormality detection system. 3. The CPU operation abnormality detection system according to claim 1, wherein the CPU receives the access prohibition information read from the storage means and switches the control to the abnormality countermeasure control.