JPH05250266A - Wrong memory write protecting device - Google Patents

Abstract

PURPOSE:To prevent held data from being destroyed by wrong write into a RAM at a controller provided with a processor. CONSTITUTION:This device is provided with a control means 201, RAM 202 composed of (x)X(n) bits, RAM 203 composed of (x)X1 bits for storing write inhibit information to the RAM 202 while being arranged in the same address space as the RAM 202, register 204 to control read/write to each RAM and a chip select signal, and gate means to invalidate data access to each RAM and a write signal to a write inhibited address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory erroneous write protection device in a system in which it is necessary to protect data held in a readable / writable storage device from being destroyed by erroneous write access.

[0002]

2. Description of the Related Art FIG. 3 shows an example of the structure of a memory erroneous write protection device for a conventional readable / writable storage device (hereinafter referred to as RAM). In the figure, 101 is a control unit including a microprocessor, 102 is a register for setting erroneous write protection for each RAM chip, and 103 to 1
Reference numeral 06 is a RAM, 107 to 110 are OR gates for outputting a write signal for each RAM chip, 111 to 114 are protection bits for setting erroneous write protection for each RAM chip in the register 102, 123, 115, 1
Reference numerals 16 and 117 denote a write signal from the control unit 101, an address bus, a data bus, a selection signal bus, and 118, respectively.
Is a selection signal for the register 102 for setting erroneous write protection, 119 to 122 are selection signals for each RAM chip, 124 to 127 are erroneous write protection control signals, 12
Reference numerals 8 to 131 denote write signals to each RAM chip.

The erroneous write protection is performed by selecting the register 102 by the selection signal 118 of the control unit 101 and writing "1" to any bit of the protection bits 111 to 114 of the register 102 via the data bus 116. .. Normally, each RAM chip 103-10
6 holds the data on the data bus 116 in the area designated by the address bus 115 at the rising edge of the write signals 128 to 131. On the other hand, protection bit 1
When "1" is written in 11 to 114, the erroneous write protection control signals 124 to 127 become "H" level and O
Each RAM chip 1 which is the output of the R gates 107 to 110
The write signals 128 to 131 to 03 to 106 are "H" regardless of the state of the write signal 123 from the control unit 101.
The level is maintained, and writing to the RAM chip becomes impossible. Therefore, even if the control unit 101 erroneously performs write access to the RAM chip for which the erroneous write protection is set, the held data is protected.

[0004]

In the configuration of the conventional erroneous write protection circuit as described above, the erroneous write protection range is R.
Since it is compatible with the AM chip, even if the range in which erroneous writing is set is small, the storage area for the size of one RAM chip must be protected by erroneous writing, and the remaining area of that RAM chip cannot be used as a work area. Therefore, the RAM is wasted and the usage is limited. Further, since the protection range is divided into blocks based on the RAM chip size, even if a part of the held data is changed, the R including the change desired address is included.
There is no choice but to cancel the erroneous write protection of the entire AM chip,
It reduced the reliability of the retained data.

The present invention solves the above-mentioned problems. It is possible to have a RAM area which is highly efficient in use and has no usage restriction due to erroneous write protection, and which is highly reliable in holding data. The purpose is to provide a device.

[0006]

In order to achieve the above object, the present invention, in addition to the first storage means having an x.times.n bit structure which is an original data holding area, has the same address space as the first storage means. Second storage means of x × 1 bit configuration for storing write permission / prohibition information to the first storage means, one register that can be set by the control unit, and the set value and control of the register. A gate means for controlling an access state to the first storage means and the second storage means of the control section by a combination of a read signal, a write signal from the control section, and a selection signal to the first storage section; Department,
Tristate gate means for avoiding collision of output data from the first storage means and the second storage means, and gate means for invalidating the write signal to the write-inhibited address of the first storage means It has a different configuration.

[0007]

In the above structure, since erroneous write protection for the RAM can be set in word units, it is possible to
Only the necessary address can be set as the erroneous write protection area without limiting the number of blocks, and the RAM area that cannot be used as the write enable area can be eliminated. Further, when it is necessary to rewrite the held data in the erroneous write protection area, only the necessary address can be released from the erroneous write protection. It is possible to avoid a decrease in reliability. In addition, since the write protected address and the held address of the write protected data are completely the same, management is easy and the write protection data can be easily confirmed by the control unit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the memory erroneous write protection device according to the present invention will be described below with reference to FIG. Reference numeral 201 in the figure denotes a control unit composed of a microprocessor, 2
Reference numeral 02 is an xxn bit configuration RAM (hereinafter referred to as RAM 202), 203 is an xx 1 bit configuration RAM (hereinafter referred to as RAM 2) arranged in the same address space as the RAM 202.
03) 204 is a register, 205 is an inverter,
206-209, 211, 212, and 236 are two-input OR
Gate, 210 is a 2-input AND gate, 213, 214
Is a tri-state gate, 215 is a latch circuit, 21
8, 219, 220 and 221 are a data bus, an address bus, a data bus least significant bit signal, an erroneous write protection control signal 222, and a clock signal 223 and 22, respectively.
Reference numerals 8, 229 and 235 denote a primary write signal, a secondary write A signal, a secondary write B signal, a tertiary write A signal, and 2 respectively.
24, 230, 231, 232 are primary read signals, secondary read A signals, secondary read B signals, tertiary read B signals, and 225, 234 are primary selection signals, secondary selection signals, 226, 227, respectively. Indicates a register signal, an inverted register signal, 233 indicates latch data of the latch circuit 215, 237 indicates a latch clock signal, and 238 indicates a register selection signal.

In the RAM 202 and RAM 203, the read signal, the write signal, and the selection signal are all "L".
It becomes active at the level. In the RAM write operation, when the selection signal is at "L" level, the data on the data bus 218 and the error write protection control signal 221 are held in the areas designated by the address bus 219 at the rising edge of the write signal. Further, the data in the RAM held in the area designated by the address bus 219 is transferred to the data bus 218 and the erroneous write protection control signal 221 while the selection signal and the read signal are both at the “L” level. Is output. The register 204 captures the state of the data bus least significant bit signal 220 at the rising of the primary write signal 223 while the register selection signal 238 is at “L” level, and outputs it as the register signal 226. The control unit 201 includes a RAM 202 and R
Register 2 to control access to the AM 203
The "H" level or the "L" level is set to 04.

First, the write access to the RAM 202 will be described. In this case, as shown in state 1 of FIG. 2, the control unit 201 sets the register 204 to the “L” level. Further, the control unit 201 outputs the “L” level primary selection signal 225 and the primary write signal 223, and holds the primary read signal 224 at the “H” level. The primary write signal 223 and the register signal 226 are input. The 2-input OR gate 206 is a low-level 2 gate.
The next write A signal 228 is output, and one of the two input terminals or both of the two inputs become the “H” level. Two-input OR gates 207, 208, 20
9 are all "H" level secondary write B signals 229,
Secondary read A signal 230 and secondary read B signal 23
1 is output respectively. Also, the RAM in which the "L" level primary selection signal 225 is directly input to the selection signal input terminal
RAM 2 to which the secondary selection signal 234, which is the output signal of the 2-input OR gate 211, to which the 203, the primary selection signal 225 and the "L" level register signal 226 are input
Both RAM No. 02 are active. The “L” level secondary write A signal 228 receives the 2-input AND gate 2
By being input to 10, the output of the tertiary read B signal 232 becomes “L” level, and the tertiary read B signal 232 becomes
RA in which the signal 232 is input to the read signal input terminal
M203 is in a read access state. Therefore, R
The data held in the area designated by the address bus 219 is output from the AM 203 as an erroneous write protection control signal 221. The erroneous write protection control signal 221 is supplied to the latch circuit 215 whose initial state is “H” level in order to eliminate the unstable state.
The output 237 of the 2-input OR gate 236 of the next write A signal 228 is latched as a latch cloak signal and output as latch data 233. Then, the tertiary write A signal 2 which is the output of the 2-input OR gate 212 to which the latch data 233 and the secondary write A signal 228 are input.
35 is input to the write signal terminal of the RAM 202.
Here, the RAM 202 has the "L" level 2 as described above.
Since the next selection signal 234 is input and is in an active state, if the tertiary write A signal 235 becomes "L" level,
The RAM 202 is in a write access state. Since the secondary write A signal 228 is at the “L” level, the effective “L” level tertiary write A signal 235 is output only when the latch data 233 is at the “L” level.
Enters the write access state. However, the latch data 2
When 33 is at "H" level, the tertiary write A signal 235
To maintain the "H" level in the non-valid state,
Even if the control unit 201 makes a write access to the RAM 202, the access is invalid. That is, when the control unit 201 makes a write access to the RAM 202, the write permission / prohibition information in the RAM 203, which is held at the same address as the write address to the RAM 202, is read and the information is at the “L” level. At this time, the write-enabled state, and at the “H” level, the write-protected state, in other words, the erroneous write-protected state. here,
Wrong write protection control signal 2 output from RAM 203
Reference numeral 21 is connected to the least significant bit of the data bus 218 via the totie state gates 213 and 214, the primary write signal 223 from the control unit 201 is at "L" level, and the set value of the register 204 is "L". In this case, the secondary write B signal 229 and the secondary read B signal
The signal 231 becomes the “H” level, the outputs of the tri-state gates 213 and 214 become the high impedance state, and the collision between the data on the data bus 218 output from the control unit 201 to the RAM 202 and the erroneous write protection control signal is avoided. To be done.

Next, the write access to the RAM 203 will be described. In this case, as shown in the state 2 of FIG. 2, the control unit 201 sets the register 204 to the “H” level. Further, similarly to the write access to the RAM 202 described above, the control unit 201 outputs the primary selection signal 225 and the primary write signal 223 of the prohibited state “L” level, and the primary read signal 224 is set to the “H” level. Hold. The register signal 226 becomes an “L” level inverted register signal 227 via the inverter 205, and the two-input OR gate 207 to which the inverted register signal 227 and the primary write signal 223 are input is an “L” level secondary write B. The 2-input OR gates 206, 208, and 209, which output the signal 229 and have either one input or two inputs of the two input terminals at the “H” level, are all at the “H” level of the 2 level. Next write A signal 228, secondary read A signal 230, and secondary read B signal 231 are output respectively. Further, the "L" level primary selection signal 22
5 is directly input to the selection signal input terminal, the RAM 203 becomes active, but the primary selection signal 225 and "H"
The RAM 202 to which the secondary selection signal 234, which is the output signal of the 2-input OR gate 211 to which the level register signal 226 is input, is inactivated. "L"
By setting the secondary write B signal 229 of the level as the write signal of the RAM 203, the RAM 203 enters the write access state, and the same secondary write B signal 229 is used as the enable signal to the tri-state gate 213, whereby the control unit Data bus 21 output by 201
8 least significant bit signal 220 on the address bus 219
It can be held as erroneous write protection control data in the area designated by.

Next, read access to the RAM 202 will be described. In this case, as shown in the state 3 of FIG. 2, the control unit 201 sets the register 204 to the “L” level. Further, the control unit 201 outputs the “L” level primary selection signal 225 and the primary read signal 224, and holds the primary write signal 223 at the “H” level. The 2-input OR gate 208, to which the primary read signal 224 and the register signal 226 are input, outputs the “L” level secondary read A signal 230 and outputs one of the two input terminals, or All of the 2-input OR gates 206, 207, 209 whose both two inputs are at the “H” level output the “H” level secondary write A signal 228, the secondary write B signal 229, and the secondary read B signal 231. Output each. Also, the "L" level primary selection signal 2
RAM 203 in which 25 is directly input to the selection signal input terminal
Then, both RAMs of the RAM 202 to which the secondary selection signal 234, which is the output signal of the 2-input OR gate 211 to which the primary selection signal 225 and the "L" level register signal 226 are input, are activated. The RAM 202 to which the “L” level secondary read A signal 230 is input to the read signal input terminal enters the read access state and outputs the data held in the RAM 202 at the address designated by the address bus 219 onto the data bus 218. here,
Since both the secondary write B signal 229 and the secondary read B signal 231 which are also enable signals to the tri-state gates 213 and 214 are “H” level, both the tri-state gates 213 and 214 are in the non-enabled state, The connection between the bus 218 and the RAM 203 is cut off, and the output data of the RAM 203 does not affect the data bus 218.

Next, the read access to the RAM 203 will be described. In this case, as shown in state 4 of FIG.
The control unit 201 sets the register 204 to the “H” level. Further, the control unit 201 outputs the “L” level primary selection signal 225 and the primary read signal 224, as in the case of the read access to the RAM 202, and
The next write signal 223 is held at "H" level. The register signal 226 becomes the “L” level inversion register signal 227 via the inverter 205, and the inversion register signal 2
The 2-input OR gate 209 to which 27 and the primary read signal 224 are input is the secondary read B signal 231 of “L” level.
Is output, and one of the two input terminals, or both of the two inputs are set to the “H” level, the two-input OR gates 206, 207, and 208 are all of the “H” level secondary. Write A signal 228, secondary write B signal 22
9 and secondary read A signal 230 are output respectively. Further, the RAM 203 to which the "L" level primary selection signal 225 is directly input to the selection signal input terminal is in an active state, but the primary selection signal 225 and the "H" level register signal 226 are input to two inputs. OR gate 211
RA to which the secondary selection signal 234 which is the output signal of
M202 becomes inactive. "L" level 2
By inputting the next read B signal 231 to the 2-input AND gate 210, the output of the third read B signal 232 becomes “L” level, and the third read B signal 2
RAM 20 in which 32 is input to the read signal input terminal
3 is in a read access state. Therefore, RAM2
From 03, the data held at the address designated by the address bus 219 is output as the erroneous write protection control signal 221. At this time, the tri-state gate 214 is "L"
When the secondary read B signal 231 of the level is set as the enable input, it is in the enable state.
The erroneous write protection control signal 221 output from
Data bus 218 through tristate gate 214
The data bus least significant bit signal 220 is read by the control unit 201. At this time, since the RAM 202 is in the inactive state as described above, the data collision can be avoided.

As described above, according to this embodiment, the RAM 1 and
RAM2 for storing write-protection information to RAM1,
Since the registers for controlling the RAMs 1 and 2 and the gate means for the RAMs 1 and 2 are provided, it is possible to prevent the held data from being destroyed by erroneous writing to the RAMs.

[0015]

As is apparent from the above embodiments, according to the memory erroneous write protection device of the present invention, the data memory can be obtained by combining the write signal from the processor, the read signal, the selection signal, and the set value to the register. Since the erroneous write protection area of can be freely set / released in word units, only the necessary address in the data memory can be set as the erroneous write protection area, and the RAM area that cannot be used as the write permission area can be eliminated.
There is an advantage that you can improve the usage efficiency of, and even if you temporarily release the erroneous write protection and change the held content, you can release only the address that needs to be changed from the erroneous write protection area. RAM like the conventional example
There is an advantage that it is possible to avoid a decrease in the reliability of the protection data due to the release of the erroneous write protection area on a chip basis.
Further, since the write enable / disable information can be held in the write / disable information memory without expanding the data width of the data memory, there is an advantage that the load on the hardware can be lightened. Further, since the address of the data memory and the address of the write / prohibition information memory are completely the same, there is an advantage that management is easy.

It is needless to say that the memory erroneous write protection can be performed in block units by allocating a memory erroneous write protection range of a plurality of words to one protection bit for memory erroneous write protection.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory erroneous write protection device according to an embodiment of the present invention.

FIG. 2 is a supplementary diagram explaining input signal conditions of RAMs 202 and 203 in FIG.

FIG. 3 is a block diagram of a conventional memory erroneous write protection circuit.

[Explanation of symbols]

201 control unit 202 x × n bit configuration RAM 203 x × 1 bit configuration RAM 204 register 205 inverters 206, 207, 208, 209, 211, 212, 2
36 2-input OR gate 210 2-input AND gate 213, 214 Tri-state gate 215 Latch circuit

Claims (2)

[Claims] 1. A control means including a processor and the like, and x × n.
A first storage means having a bit structure which is readable and writable by the control means; and a second readable storage means having an x × 1 bit structure which stores write enable / disable information for the first storage means. A register that can be set by the control means, a read signal from the control means,
The access state from the control means to the first storage means and the second storage means is controlled by a combination of a write signal, a selection signal of the first storage means, and a set value of the register. Gate means, gate means for avoiding a collision between output data of the control means and output data of the second storage means, and a gate for invalidating a write signal to a write-inhibited address of the first storage means Means for reading the data held in the second storage means at the same time as the write access to the first storage means, and controlling the write signal to the first storage means according to the value of the read data. Write error protection device. 2. A second storage means is readable and writable by the control means, the first storage means and the second storage means are arranged in the same address space, and the data bus width is set from the control means. Without expanding the data width of the first storage means, the normal data is stored in the first storage means, and the normal data is stored in the second storage means at the same address as that of the first storage means. The write permission / prohibition information corresponding to the address of the first storage means is made writable, and is held by the control means in the normal data held in the first storage means and in the second storage means. Write permission to the first storage means /
The memory erroneous write protection device according to claim 1, wherein the prohibition information can be read.