JPS61213938A - Generation system for address coincidence signal - Google Patents

Abstract

PURPOSE:To reduce the amount of hardware to be added by providing a means which diverts redundant bits of an RAM to an address coincidence signal and specifies the leading address of firmware and an optional address of the RAM externally. CONSTITUTION:The RAM reading and writing firmware transfers an address that an accumulator register 14 to a register file and transfers it to the RAM 2 through an address bus 19 and a switch 3 to read the corresponding address, which is inputted to the accumulator register 14. The contents of the accumulator register 14 are read out and then written in the RAM 2 after logic 1 is written in a bit of a register file for an address coincidence signal. The bit for the address coincidence is read in an address coincidence detecting circuit 16 and 1 is outputted as the address coincidence signal when a decoder 10 indicates access to the RAM 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention provides an address match signal generation system, in particular, a method for generating an address match signal, in order to facilitate maintenance of a microprogram controller. This invention relates to an address match signal generation method for generating a match signal tQ.

(Prior Art) With the rapid development of integrated circuit technology in recent years, devices using integrated circuits have become increasingly sophisticated and multifunctional. However, as a result, such devices have become highly complex, making failure analysis difficult. Microprogram controllers are no exception.

Therefore, when starting up a microprogram control device, a fault diagnosis program is first used to perform a fault diagnosis, and if a fault is detected, a countermeasure is taken before using the microprogram control device. In addition, during use, the micro-m full word address, memory request source,
All status history memory such as memory addresses, memory reply signals, and memory wait signals are written sequentially in synchronization with the execution of microinstructions, and when a stop condition such as a failure is detected in the microprogram control device, for example, the service A processor or the like reads out the state history memory, analyzes the read data, takes measures against the fault, and if necessary executes an appropriate fault diagnosis program to proceed with the fault analysis.

Collecting this kind of status history is an effective measure against failures, but
A simpler fault diagnosis method that does not require a state history memory is to generate an address match signal t-i at the desired address of the microprogram, and use this as a synchronization signal to calculate the waveforms of key points in the circuit of the microprogram control device. There are systems in which failures are observed using a synchroscope or the like, or the operation of the microprogram control device is stopped and failure analysis is performed based on the state of important parts of the device at that time.

Conventionally, this type of address match signal is generated when an access address to a microprogram storage memory and a desired address are compared outside the microprogram control device and one of the two addresses match.

(Problem to be Solved by the Invention) This conventional method requires a register to set the desired address and a comparator to compare the two addresses, but the microprogram storage The address bit length of memory is usually about 10 bits, so the registers and comparators must also be of that bit length.
There is a problem that the amount of hardware increases.

Therefore, an object of the present invention is to provide an address match signal generation system that minimizes the amount of node hardware to be added.

(Means for Solving the Problems) The method of the present invention is such that a predetermined one bit of a read/write memory (hereinafter referred to as RAM) for storing a microprogram is reserved for an address match signal, RAM
1. Firmware to be accessed for updating and means for externally specifying the starting address of the firmware and an arbitrary address in RAM are provided, and when maintaining the microprogram control device, the desired address in RAM is specified externally and the firmware is updated. By activating the microprogram, a predetermined bit is updated with predetermined binary information so that writing can be performed at the same location, and an address match signal is obtained from the binary information read out while the microprogram is being executed. do.

(Function) In the present invention, the RAM for storing microprograms
focuses on the fact that a certain number of bits common to each address are usually left unused.

One of these bits is reserved for the address match signal, the microprogram is read externally by the firmware during maintenance, and the address match signal pit at the desired address is set to a predetermined binary value using an existing circuit. The information is updated and written to the same address by firmware, and the address match signal is obtained from the address match signal pit at this address read during execution of the microprogram.

(Example) FIG. 1 shows an example of the present invention. Referring to FIG. 1, this embodiment has a read-only memory (hereinafter referred to as ROM) 1
, RAM 2, two switchers 3 and 4, counter 5, micro instruction address register 6, stack memory 7, arithmetic unit 8, trap control circuit 9, two decoders 10 and 11, and micro instruction register 12
, a microprogram controller consisting of a microinstruction read register 13 , an accumulation register 14 , a driver 15 , and an address match Yokota circuit 16 , a service bus 17 . It is connected to data bus 18 and address bus 19.

RUMl is 1 piece of initial diagnostic firmware for initial diagnosis of the microprogram control device, RAM write firmware for initial loading of the microprogram into RAM2, and RAM read/write for updating the microprogram loaded in RAM2. Firmware and firmware for service processing such as register reading in response to requests from the service processor are stored in advance.

RAM2 is a memory used to store microprograms, and each address contains a microinstruction bit, a parity bit, and one bit for an address match signal (logic ``0'' is written as an initial value). However, since the RAM 2 is generally a general-purpose memory having a bit width equal to or larger than the microinstruction word length, one bit is not purposely added.

ROM1 and RAM2 are accessed in parallel by the output of the switch 3, and each read data is supplied to the switch 4, but the decoder 10 selects OMI or RAM2 from the output of the switch 3. By decoding the data and outputting it to the switch 4, only one of the bladder evacuation data is accepted into the switch 4. Switcher 4
The output (microinstruction) of microinstruction register 12
and the microinstruction read register 13.

The microinstruction read register 13 is for outputting the output of the switch 4 to the data bus 18, and the accumulation register 14 is for accumulating the data on the data bus 18 and for reading the data from the service processor via the service bus 17t. (
It is now possible to exchange data (in a broad sense) with (not shown).

The output (microinstruction) of the microinstruction register 12 is supplied to the decoder 11, the driver 15, the arithmetic unit 8, and the switch 3. Decoder 11 decodes the output of microinstruction register 12 and generates command CMDi. This command CMD is transmitted to and executed during the execution of a microinstruction (not shown) in the microprogram control device, and is also supplied to various parts of the circuit shown in FIG. 1 to control the circuit. Driver 15 is for enhancing the output of microinstruction register 12.

In a normal micro-sequence, when the result of decoding of a micro-instruction in the decoder 11 is that it is not a jump instruction, or even if it is a jump instruction, the jump fails because the conditions for jumping are not met, etc. The microsequence address read out aloud (output from the switch 3) is incremented by a counter 5, and this incremented by 9 microsequence address is supplied to the switch 3 via the memory address register 6.

The trap control circuit 9 is for storing the trap destination address in response to the node hardware state when the command CMD is executed in the microinstruction execution unit, and the stack memory 7 is for storing the trap destination address at the time of jump or trap. This is to set the contents held in the memory address register 6 in preparation for return after a jump or trap. Further, the arithmetic unit 8 is used to calculate a jump destination address by calculating the address portion of the contents held in the microinstruction register 12 and the contents held in the memory address register 6 as instructed by the command CMD.

When the microinstruction instructs a relative jump (established), absolute jump, trap, return, or external address seratra, the switch 3 selects the output of the arithmetic unit 8 and the address part of the contents held in the microinstruction register 12, respectively. , the output of the trap control circuit 9, the output of the stack memory 7, or the address on the address bus 19.

The service bus 17 is connected to the service processor, and is connected to the memory address register 6 from the service processor.
You can set and read microinstructions from the microinstruction register.

When the system is started up, the initial diagnostic firmware stored in the OMI is first started.

An initial diagnosis of the microprogram controller is performed. As a result, if no abnormality is detected, then the ROMI
The RAM write firmware stored in the RAM 2 is activated, and a microprogram is written into the RAM 2 from the outside via the address bus 19 and the data bus 18.

Initial firmware, RAM write firmware, and microprogram startup are performed by each RUMl.
Alternatively, this can be done by setting the storage start address in the RAM 2 in the memory address register 6 by the service processor, and setting the command CMD so that the switch 3 accepts the output of the memory address register 6.

When the microprogram is started, each microinstruction of the microprogram stored in the RAM 2 is executed by the microinstruction execution section, and the switch 3 performs a switching operation in response to the microinstructions as described above. When updating the microprogram, the execution of the microprogram is stopped, the service processor sets the storage start address of the RAM read/write firmware in ROM 1 in the memory address register 6, and the switch 3
The RAM read/write firmware is activated by setting the command CMD'i so that it receives the output of the memory address register 6.

I(, AM read/write firmware is activated not only when the microinstruction section is updated but also when the address match signal bit is sent or changed.The address match signal bit is activated during maintenance of this microprogram control device.
It is used to generate the synchronization signal t% or to stop the operation of the microprogram controller, and only the microinstruction steps according to the intended purpose, e.g. logic "1"
Write.

Such an update is performed as follows.

First, from the service processor to the accumulation register 14
Set the address of 1%AM2 to be updated in , and then start the LAM read/write firmware described above. The RAM read/write firmware transfers the address held by the Achim register 14 at this time to a register file (general working register, not shown), and transfers this address to the A key register via the address bus 19 and the switch 3.
It is transferred to M2, the corresponding address tone is read, and inputted to the accumulation register 14 via the microinstruction read register 13 and data bus 18. Furthermore, the accumulation register 14 is read out and transferred to the register file, where logic 11'' is written to the address match signal bit mentioned above and written to the RAM 2 via the data bus.At this time, the ftAM20 address is This is the address set in the accumulation register 14 by the processor.

The intended purpose can be achieved by repeating the write operation of the address match signal as described above as many times as necessary. For example, if you want to observe the waveforms of key points in the circuit of a microprogram control device using a synchroscope, you will need to write address match signals to multiple addresses, and you will only have to stop the operation of the microprogram control device. In that case, only address 1 is sufficient.

Now, as the microprogram in which the address match signal is written is executed in this way, and when the address whose address match signal bit is ul'' is read, the address match detection circuit 16 outputs fil''. That is,
The microinstruction bit of the read data of RAM2 is read out to the microinstruction register 4, but the address match signal bit is read out to the address match detection circuit 16, and if the decoder 10 indicates access to RAM2, the address match signal bit is read out to the microinstruction register 4. '1' is outputted to the outside as the match signal AEQ. Therefore, the address match detection circuit 1
6 can be done with a two-person AND gate.

(Effects of the Invention) According to the present invention, as described above, surplus bits of RAM are diverted to address match signals, and the RAM read/write firmware is configured so that address match signals can be written using all existing circuits. By creating this, it is possible to obtain an address match signal generation method that requires an extremely small amount of additional hardware.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention. 1...Read-only memory (ROM), 2...
... Read and write memo IJ (RAM) at any time, 3.4...
...Switcher, 5...Counter, 6...
...Memory address register% 7...Stack memory, 8...Arithmetic unit, 9...Trap control circuit% 10.11...Decoder, 1
2...Microinstruction register, 13...
・Micro instruction read register, 14...Accumulation register, 15...Driver, 16...
. . . address match detection circuit, 17 . . . service bus, 18 . . . data bus. 19...Address bus.

Claims (1)

[Scope of Claims] Firmware that reserves a predetermined bit of a memory that can be read and written at any time to store a microprogram for an address match signal, and that is accessed to update the memory that can be read and written at any time; and a means for externally specifying a starting address of the memory that can be read and written at any time, and a means for externally specifying a desired address of the memory that can be read and written at any time during maintenance of the microprogram control device, and starting the firmware. By doing so, the predetermined bit is updated with predetermined binary information so that it can be written to the same location, and the second bit read out while the microprogram is being executed.
An address match signal generation method characterized in that an address match signal can be obtained from value information.