JPS60195641A - Microprogram controlling device - Google Patents

Abstract

PURPOSE:To obtain a microprogram controlling device from which the quantity of hardware can be reduced, by commonly using a RAM for state hysteresis data and fault diagnostic program. CONSTITUTION:When a stopping condition such as fault is detected in a microprogram controlling device, the controlling device is stopped and the program reading out sequence from a ROM1 and state hysteresis data writing sequence to a RAM2 are also stopped. At this time, a log routine stored in the ROM1 is started and a swtich 7 is switched to a receive the output of the RAM2. A microinstruction CMD sets an FF17 to a set condition and a RAM controlling circuit 18 outputs the designation signal of a minum access mode to a counter 3. Accordingly, the counter 3 successively subtracts ''1'' from its holding content at the time of stoppage and the address of the RAM2 designated by the holding content of the counter 3 is read out by an external service processor, etc., through the switch 7, a reading out register 21, and data bus 9.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a microprogram control device, and more particularly, to a microprogram control device having a function of collecting and storing state history data for fault analysis and a function to be tested by a fault diagnosis program. Regarding.

(Technical background) With the rapid development of integrated circuit technology in recent years, devices using integrated circuits have become increasingly sophisticated and multifunctional. However, as a result, such devices have become highly complex, making failure analysis difficult. Microprogram controllers are no exception.

Failure analysis of microprogram control devices is often performed by collecting and storing state history data and executing a failure diagnosis program. When the microprogram control device is started up, a fault diagnosis program is first loaded into the test memory, the fault diagnosis program is used to diagnose the microprogram control device, and when a fault is detected, the device is treated. Operate the microprogram control device.

When the microprogram controller is in operation, for example, microinstruction word addresses, memory request sources within the microprogram controller.

Memory addresses, memory reply signals, memory wait signals, channel numbers, etc. are stored as state history data in the state history memory, synchronously and sequentially with the execution of microinstructions.
Write it down and remember it.

When a stop condition at the time of a failure is detected in the microprogram control device, writing of the state history data is stopped and an external device such as a service processor writes the state history memo I.
Read J k and analyze it. If the results of this analysis determine that sufficient measures can be taken against the failure,
There is no need to load a fault diagnosis program. If the state history data alone is insufficient to take a sufficient response, an appropriate fault diagnosis program is loaded into the test memory based on the analysis results of the state history data to perform fault analysis.

(Prior Art) In this type of conventional microprogram control device, the test memory and the state history memory are separate memories;
The disadvantage is that it requires a large amount of hardware.

(Object of the Invention) An object of the present invention is to provide a microprogram control device that reduces the amount of hardware.

(Structure of the Invention) The device of the present invention is a microprogram control device, and includes a control memory for storing a microprogram, and state history data of the microprogram control device or a failure for the microprogram control device supplied from the outside. a memory for storing a diagnostic program; an access mode control means set or reset by microinstructions of the microprogram; and all sets of access addresses to the memory when the memory is used for the state history data. and address generation means that generates in a mode corresponding to the state and reset state.

address switching means for switching between the access address and an access address to the memory given from the outside when the memory is used for the fault diagnosis program and supplying the memory to the memory; and the state history data and the fault diagnosis program. write data switching means for switching between and supplying write data to the memory;

The present invention is characterized by further comprising read data switching means for switching and outputting the microprogram read from the control memory and the fault diagnosis program read from the memory.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, this embodiment has a read-only memory (R
OM) 1, read/write memory (RAM) 2, two counters 3 and 10, four switches 4, 5, 6, and 7, an address bus 8, a data bus 9, and a memory address register. 11, return memory 12, and adder 1
3, a trap control circuit 14, two decoders 15 and 23, two 7-lip 70 tubes 16 and 17, a RAM control circuit 18, a microinstruction register 19, a decoder 19, an accumulation register 20, and a read tracer. This is a microprogram control device consisting of a register 21 and a buffer gate 22.

ROM1 stores in advance a microprogram for controlling the microprogram system device, and the RAM
2 switches between the access address to ROM 1 as state history data and the fault diagnosis program supplied from the outside, and stores only one of them.

When starting up the system, first a diagnostic program load routine stored in RQMI is activated. The microinstruction CMD at the beginning of the diagnostic program load routine causes the switch 4 to input the address signal from the address bus 8. Since this address specifies RAM2't-, the decoder 15 outputs a logic "0", thereby.

RAM? 1Ill-Circuit 18 receives microinstruction words (constituting the diagnostic program) from switch output 40 and data bus 9, which are the outputs of switch 4 and switch 5 and 6, respectively.
Outputs a signal that switches to accept.

Also, the %RAMl1ill@circuit 18 responds to the microinstruction CMD of the diagnostic program load routine to write the write instruction 180'! The diagnostic program (in this case, the initial test routine) from the data bus 9 is written into the RAM 2 by outputting it to the rRAM2.

When the writing of the initial test routine to the RAM 2 is completed, the initial diagnosis of the microprogram control device is executed based on this initial test routine. Based on the results of this initial diagnosis, if a fault is detected, necessary measures are taken, after which the microprogram control unit is activated and the command CMD causes iJR to be displayed on counter 3.
The start address of AM2 is set.

When the microprogram controller is activated, the switch output 40 specifies the address of ROM1 in response to the microinstruction CMD, and the decoder 15 outputs the logic "
1". Based on this result, the RAM control circuit 18
outputs a signal to the switch 7 so that the switch 7 accepts the output of the ROM1.

Microinstruction words are read out one after another from the ROM 1 to the microinstruction register 19, and the decoder 23 decodes the microinstruction words and transmits the microinstruction CMDI to the microinstruction execution unit (not shown). Microinstruction CMD is executed.

At this time, RAM! When the 7 lip-flop 16 is set to the set state in response to the microinstruction CMD, the control circuit 18Fi sends a signal to the switch 5 and 6 to enable the switch 5 and 6 to accept the output of the counter 3 and the output of the switch 40, respectively. 6 and the write instruction 180iRAM2. Also, at this time, the RAM control circuit 18Fi outputs a sidewalk-like signal to the counter 3 from the top address of the RAM 2 in synchronization with the reading of the ROMI. Therefore, the current access address to the ROM 1 is written to the address of the RAM 2 specified by the counter 3 in response to the write instruction 180. In this way, by setting the flip-flop 16, the access address iR of the microinstruction word to be traced as state history data in the microprogram is set.
By writing to AM2 and setting the flip 70 knob 16 to the reset state, access addresses that do not require tracing, such as when waiting for an interrupt or during a log routine, can be written to RAM2.
You can prevent it from being written to.

Isn't the microinstruction CMD a jump instruction?

Or, even if it is a jump instruction, in a normal microsequence when the jump fails due to the conditions for jumping not being met, the microinstruction CMD
i The read microsequence address (switcher output 40) is incremented by the counter 10, and this incremented microsequence address is sent to the ROMI and the switcher 6 via the memory address register 11 and the switcher 4. The same process as above is repeated.

Microinstruction is absolute jump, relative jump (when established)
, when instructing a trap or return, the switch 4 selects the address part of the contents held in the microinstruction register 19, the result of the operation in the adder 13 of the address part and the contents held in the memory address register 11, and the trap. The output of the control circuit 14 or the output of the recovery memory 12 is accepted. In the trap control circuit 14, a trap destination address is set in response to the node hardware state at the time of execution of the microinstruction CMD in the microinstruction execution unit.
In the return memory 12, the contents held in the memory address register 11 at this time are set at the time of a jump or a trap.

RAMZtl All such switch outputs 40, the decoder 15 outputs '1' and the key write instruction 180
In response to this, the counter 3 writes to the address specified. In such a state, if a stop condition such as a failure is detected in the microprogram control device, the microprogram control device will stop and the ROMI
The sequence of reading the microprogram from the RAM 2 and writing the state history data to the RAM 2 also stops.

At this time, the log routine stored in ROMI is started, and the microinstruction C at the beginning of this log routine is activated.
MD causes the switch 7 to switch to accept the output of the RAM 2. At this time, the microinstruction CMD is the flip 70 tube 17ft which has been in the reset state so far.
Set state. Based on this result, the RAM control circuit 18 outputs a signal for instructing the counter 3 to enter the negative access mode. Therefore, the counter 3 sequentially decrements the held contents by 1 from the held contents when the counter 3 is stopped, and the RA specified by each held contents is
The address of M2 can now be read out to an external device, such as a service processor, via the switch 7, the read register 21, and the data node 9.

Note that when the flip-flop 17 is in the reset state, the switch 5 accepts the output of the switch 40, so the address signal input from the console (not shown) is transmitted to the RAM 2 via the address bus 8, and the RAM
2i reading is also possible.

The memory contents of RAM2 read externally at this time are as follows:
RQ when the microprogram controller was operating
This is the access address to Ml.

By investigating this sequentially from the time of stoppage, it is possible to contribute to the investigation of the cause of the above-mentioned stoppage.

If the cause of the stoppage can be ascertained simply by examining such state history data, and necessary recovery measures are taken, the microprogram control device can be put into operation again. In addition, when examining the state history data alone is insufficient, an appropriate fault diagnosis program is externally loaded into RAM 2 to perform fault diagnosis of the microprogram control device in the same manner as when using the initial test routine described above. It will be done.

Note that the accumulation register 20 is for accumulating the data on the data bus 9, and the buffer gate 2
2 is for strengthening the output power.

In this embodiment, the RAM 2 stores only the state history data or the fault diagnosis program, but it is not possible to store it in the ROMI (relatively fluid) by providing a storage area for the microprogram (relatively fluid). Examples can be implemented without changing the drawings for the previously described embodiments.

In addition, in this embodiment, as the state history data, R
Although the access address to OMI is collected, the present invention is of course not limited to this, and as described above, other signals synchronized with the execution of the microprogram may be collected. .

(Effects of the Invention) According to the present invention, by employing the above configuration, the RA
Since M can be shared for state history data and fault diagnosis programs, the amount of hardware can be significantly reduced. Furthermore, since the access mode to the RAM when writing and reading state history data can be switched in correspondence with the set state and reset state of the flip 70 knob, the amount of hardware can be further reduced.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the invention. l...read-only memory (ROM), 2.・・・
,... Read-write memory (RAM), 3.10...
...Counter, 4,5.6.7...Switcher,
8...address bus, 9...data bus, 11...memory address register, 12...
...Return memory, 13...Adder, 14
...Trap control circuit, 15.23...
Decoder, 16.17...Flip 70 knobs,
18...RAM control circuit, 19...Micro instruction register, 20...Accumulation register, 21...Read register, 22...
...Buffer gate, 40...Switcher output, 1
80...Write instruction, CMD...Command. Agent: Patent Attorney Shinatsu Uchihara / l

Claims (1)

[Claims] In a microprogram control device, τ, an Ill fit memory for storing a microprogram, and at least state history data of the microprogram control device and a failure diagnosis program for the microprogram control device supplied from the outside. an access mode control means set or reset by a microinstruction of the microprogram; address generating means that generates in a mode corresponding to a set state and a reset state, and an access address to the memory that is given from the outside when the access address and the memory are used for the fault diagnosis program. address switching means for switching between the state history data and the failure diagnosis program and supplying the memory to the memory; A microprogram control device comprising read data switching means for switching and outputting a program.