JPS63114319A - 出力回路 - Google Patents

出力回路

Info

Publication number
JPS63114319A
JPS63114319A JP61259867A JP25986786A JPS63114319A JP S63114319 A JPS63114319 A JP S63114319A JP 61259867 A JP61259867 A JP 61259867A JP 25986786 A JP25986786 A JP 25986786A JP S63114319 A JPS63114319 A JP S63114319A
Authority
JP
Japan
Prior art keywords
output
input
signal
output circuit
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61259867A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0517729B2 (enrdf_load_stackoverflow
Inventor
Michiya Nakamura
中村　道也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61259867A priority Critical patent/JPS63114319A/ja
Publication of JPS63114319A publication Critical patent/JPS63114319A/ja
Publication of JPH0517729B2 publication Critical patent/JPH0517729B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microcomputers (AREA)
  • Logic Circuits (AREA)
JP61259867A 1986-10-30 1986-10-30 出力回路 Granted JPS63114319A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61259867A JPS63114319A (ja) 1986-10-30 1986-10-30 出力回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61259867A JPS63114319A (ja) 1986-10-30 1986-10-30 出力回路

Publications (2)

Publication Number Publication Date
JPS63114319A true JPS63114319A (ja) 1988-05-19
JPH0517729B2 JPH0517729B2 (enrdf_load_stackoverflow) 1993-03-10

Family

ID=17340060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61259867A Granted JPS63114319A (ja) 1986-10-30 1986-10-30 出力回路

Country Status (1)

Country Link
JP (1) JPS63114319A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0651510A1 (en) * 1993-10-29 1995-05-03 STMicroelectronics S.r.l. Input/output stage adapted to operate with low and high voltages
EP0575124A3 (en) * 1992-06-15 1996-07-24 Fujitsu Ltd Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
KR100482367B1 (ko) * 2002-08-09 2005-04-13 삼성전자주식회사 반도체 메모리장치의 데이터 출력버퍼 및 그 데이터출력방법

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103536A (en) * 1980-01-23 1981-08-18 Hitachi Ltd Mis output circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103536A (en) * 1980-01-23 1981-08-18 Hitachi Ltd Mis output circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6720804B2 (en) 1992-05-15 2004-04-13 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
EP0575124A3 (en) * 1992-06-15 1996-07-24 Fujitsu Ltd Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US5557221A (en) * 1992-06-15 1996-09-17 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
EP0883247A3 (en) * 1992-06-15 1999-07-21 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6034555A (en) * 1992-06-15 2000-03-07 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6492846B1 (en) 1992-06-15 2002-12-10 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6707325B2 (en) 1992-06-15 2004-03-16 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6737893B2 (en) 1992-06-15 2004-05-18 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
US6744300B2 (en) 1992-06-15 2004-06-01 Fujitsu Limited Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
EP0651510A1 (en) * 1993-10-29 1995-05-03 STMicroelectronics S.r.l. Input/output stage adapted to operate with low and high voltages
KR100482367B1 (ko) * 2002-08-09 2005-04-13 삼성전자주식회사 반도체 메모리장치의 데이터 출력버퍼 및 그 데이터출력방법

Also Published As

Publication number Publication date
JPH0517729B2 (enrdf_load_stackoverflow) 1993-03-10

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