JPS6310896B2 - - Google Patents

Info

Publication number
JPS6310896B2
JPS6310896B2 JP557380A JP557380A JPS6310896B2 JP S6310896 B2 JPS6310896 B2 JP S6310896B2 JP 557380 A JP557380 A JP 557380A JP 557380 A JP557380 A JP 557380A JP S6310896 B2 JPS6310896 B2 JP S6310896B2
Authority
JP
Japan
Prior art keywords
film
silicon
silicon dioxide
mask
dioxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP557380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56103443A (en
Inventor
Toshuki Ishijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP557380A priority Critical patent/JPS56103443A/ja
Publication of JPS56103443A publication Critical patent/JPS56103443A/ja
Publication of JPS6310896B2 publication Critical patent/JPS6310896B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP557380A 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device Granted JPS56103443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP557380A JPS56103443A (en) 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP557380A JPS56103443A (en) 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device

Publications (2)

Publication Number Publication Date
JPS56103443A JPS56103443A (en) 1981-08-18
JPS6310896B2 true JPS6310896B2 (de) 1988-03-10

Family

ID=11614956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP557380A Granted JPS56103443A (en) 1980-01-21 1980-01-21 Production of element isolation structure for semiconductor device

Country Status (1)

Country Link
JP (1) JPS56103443A (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873163A (ja) * 1981-10-27 1983-05-02 Toshiba Corp Mos型半導体装置
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US4927780A (en) * 1989-10-02 1990-05-22 Motorola, Inc. Encapsulation method for localized oxidation of silicon
US6306726B1 (en) * 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide

Also Published As

Publication number Publication date
JPS56103443A (en) 1981-08-18

Similar Documents

Publication Publication Date Title
EP0034910B1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung und so hergestellte Vorrichtung
JP3191693B2 (ja) 半導体記憶装置の製造方法
US4419813A (en) Method for fabricating semiconductor device
JPH0355984B2 (de)
JPH1126597A (ja) 半導体装置の製造方法
US4532696A (en) Method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate
JPS622465B2 (de)
US4151631A (en) Method of manufacturing Si gate MOS integrated circuit
JPH0638496B2 (ja) 半導体装置
JPH05206451A (ja) Mosfetおよびその製造方法
GB2080024A (en) Semiconductor Device and Method for Fabricating the Same
JPH06163532A (ja) 半導体素子分離方法
JPS6310896B2 (de)
EP0233791A2 (de) Isolierter Gatter-Feldeffekttransistor und dessen Herstellungsverfahren
JPH0116018B2 (de)
JPS60241261A (ja) 半導体装置およびその製造方法
JPS6310897B2 (de)
JPS6333868A (ja) Mis型電界効果トランジスタの製造方法
JPS603157A (ja) 半導体装置の製造方法
JPH07115195A (ja) Mosトランジスタ及びその製造方法
JPS6092666A (ja) Misトランジスタの製造方法
JP3848782B2 (ja) 半導体装置の製造方法
JPS641942B2 (de)
JPS6129151B2 (de)
KR20020030338A (ko) 반도체 장치 제조방법