JPS63107093A - Manufacture of conducting circuit - Google Patents
Manufacture of conducting circuitInfo
- Publication number
- JPS63107093A JPS63107093A JP25221286A JP25221286A JPS63107093A JP S63107093 A JPS63107093 A JP S63107093A JP 25221286 A JP25221286 A JP 25221286A JP 25221286 A JP25221286 A JP 25221286A JP S63107093 A JPS63107093 A JP S63107093A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- hollow
- conductive
- conductive circuit
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000011521 glass Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 32
- 238000002425 crystallisation Methods 0.000 claims description 16
- 230000008025 crystallization Effects 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000010304 firing Methods 0.000 claims description 8
- 239000011796 hollow space material Substances 0.000 claims description 6
- 229910000831 Steel Inorganic materials 0.000 claims description 5
- 239000010959 steel Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000000843 powder Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 229910001220 stainless steel Inorganic materials 0.000 claims description 2
- 239000010935 stainless steel Substances 0.000 claims description 2
- 229910000272 alkali metal oxide Inorganic materials 0.000 claims 1
- 229910000287 alkaline earth metal oxide Inorganic materials 0.000 claims 1
- 150000004703 alkoxides Chemical class 0.000 claims 1
- 150000007942 carboxylates Chemical class 0.000 claims 1
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 84
- 238000007639 printing Methods 0.000 description 16
- 239000010931 gold Substances 0.000 description 15
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 230000003746 surface roughness Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 239000011230 binding agent Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000005338 heat storage Methods 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MXRIRQGCELJRSN-UHFFFAOYSA-N O.O.O.[Al] Chemical compound O.O.O.[Al] MXRIRQGCELJRSN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は導電回路の製造方法に関するものであり、特に
基板としてホーロ基板を用い、このホーロ層上にサーマ
ルヘッド、ノ・イブリッドＩＣ回路などに用いる導電性
電極回路を形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a conductive circuit, and in particular, a hollow substrate is used as the substrate, and a conductive circuit for use in thermal heads, non-bridled IC circuits, etc. is formed on the hollow layer. The present invention relates to a method of forming a sex electrode circuit.
従来の技術
従来絶縁基板上に回路を形成する方法としては、０表面
をグレーズ処理したアルミナ基板上に金。BACKGROUND OF THE INVENTION Conventional methods for forming circuits on insulating substrates include forming gold on an alumina substrate whose surface is glazed.
銅、クロムなどを蒸着、スパッタリングなどの薄膜プロ
セス技術を用いて膜形成し、フォトリノエツチングして
回路パターンを形成する方法、■前記基板上に厚膜用ペ
ーストを印刷焼成して回路パターンを形成する方法、■
鋼板の表面にホーロ層を形成したホーロ基板上に薄膜回
路を形成する方法、■前記ホーロ基板上に前肥厚膜用ペ
ーストを印刷焼成して回路パターンを形成する方法が用
いられている。A method of forming a film using thin film process technology such as evaporation or sputtering of copper, chromium, etc., and forming a circuit pattern by photoreno etching. ■ Forming a circuit pattern by printing and baking a thick film paste on the substrate. How to do, ■
A method is used in which a thin film circuit is formed on a hollow substrate in which a hollow layer is formed on the surface of a steel plate, and a method is used in which a circuit pattern is formed by printing and baking a pre-thickened film paste on the hollow substrate.
このような厚膜、薄膜形成による回路製造法について、
サーマルヘッドを例にあげて以下に説明する。Regarding circuit manufacturing methods using thick and thin film formation,
This will be explained below using a thermal head as an example.
第６図は上記■の方法によるもので、アルミナ基板１０
０の表面のガラスグレーズ層１０１を有する基板上にＴ
ａ５ｉ薄膜抵抗体層１０２ 、 ＣｒＣｕ電極薄膜層１
０３，５ｉｎ２酸化防止膜１ｏ４゜ＳｉＣ耐摩耗層１０
５から構成され、１０２，１０３層はフォトリンエツチ
ング法によシロ本／Ｆ−１２本、４の微細パターン形成
がされる。ガラスグレーズ層１０１は微細パターン形成
のために要求される表面平滑性（Ｒａ＜０．１ 、ｉ＋
ｍ ）および、発熱印字効率を高めるだめの蓄熱層の両
方の目的を満たすためのものである。Figure 6 shows the result of the method (■) above, with an alumina substrate 10
T on a substrate with a glass glaze layer 101 on the surface of
a5i thin film resistor layer 102, CrCu electrode thin film layer 1
03.5in2 Anti-oxidation film 1o4゜SiC wear-resistant layer 10
The 102nd and 103rd layers are formed with a fine pattern of white/F-12 and 4 layers by photoretching. The glass glaze layer 101 has surface smoothness (Ra<0.1, i+
m) and as a heat storage layer for increasing heat-generating printing efficiency.
第７図は、上記■の方法によるもので、ステンレス板１
１０の表面のホーロ層１１１を有する基板上に、Ａｕ粉
末とガラスフリットと有機バインダとから成るインキ、
またはＡｕのメルカプチドなどいわゆるメタルオルガニ
ックを溶剤に溶かしたインキを印刷し、焼成することに
よりＡｕ電極層１１２を形成し、この上に同じくＲｕＯ
２とガラスフリットとバインダとから成る混合ペースト
を印刷焼成し抵抗体層１１３を形成し、さらに５１０２
粉末とバインダとから成るインキを印刷焼成し耐摩耗層
１１４を形成したものである。金電極の微細パターン形
成のために７オトリンエソチング法を用いることもある
。Figure 7 shows the stainless steel plate 1 obtained by the method (■) above.
On a substrate having a hollow layer 111 on the surface of No. 10, ink consisting of Au powder, glass frit, and an organic binder,
Alternatively, the Au electrode layer 112 is formed by printing an ink containing so-called metal organic such as Au mercaptide dissolved in a solvent and baking it.
A mixed paste consisting of 5102, glass frit, and a binder is printed and fired to form a resistor layer 113.
The wear-resistant layer 114 is formed by printing and baking ink made of powder and binder. The 7-otrine etching method is sometimes used to form fine patterns of gold electrodes.
発明が解決しようとする問題点
ところでこのような従来法にはいくつかの問題点がある
。従来用いられている薄膜形成法は、設備コストが高く
生産性も悪く、製造コストが高くなる。微細パターンを
形成する方法としては有利だが、コスト的には厚膜印刷
焼成法より不利になる。厚膜法は製造コストが低くなる
が、微細パターン形成基板としてグレーズアルミナを用
いた場合、インキの焼成温度の上限がグレーズ層の軟化
点により制限されるために、得られた電極膜、抵抗膜の
特性が充分なものにならない。６本〜８本／１１１１の
微細パターン形成のためにはホーロ基板はその表面粗さ
、うねり、ピンホールなどの点で解決すべき問題が多く
、単純に従来のホーロ基板の表面に厚膜ペースト印刷、
焼成しただけでは満足な回路を得ることができない。Problems to be Solved by the Invention However, there are several problems with such conventional methods. Conventionally used thin film forming methods have high equipment costs and poor productivity, resulting in high manufacturing costs. Although this method is advantageous as a method for forming fine patterns, it is more disadvantageous than the thick film printing and firing method in terms of cost. Although the thick film method has lower manufacturing costs, when glazed alumina is used as the fine pattern forming substrate, the upper limit of the firing temperature of the ink is limited by the softening point of the glaze layer, so the resulting electrode film and resistive film characteristics are not sufficient. In order to form a fine pattern of 6 to 8 lines/1111 lines, hollow substrates have many problems that need to be solved in terms of surface roughness, waviness, pinholes, etc., and it is simply necessary to apply thick film paste on the surface of a conventional hollow substrate. printing,
It is not possible to obtain a satisfactory circuit just by firing.
本発明は、上記のような従来の回路基板の種々の問題点
を解決するためのもので、特に上記［相］の方法のホー
ロ基板上に印刷焼成法により導電層を形成して導電回路
を形成しようとするものであシ、特に、表面粗度の低い
ホーロ層の上に微細導電回路パターンを形成する方法に
関するものである。The present invention is intended to solve the various problems of conventional circuit boards as described above, and in particular, to form a conductive layer on a hollow substrate using the above-mentioned [phase] method by printing and baking to form a conductive circuit. In particular, the present invention relates to a method for forming a fine conductive circuit pattern on a hollow layer having a low surface roughness.
問題点を解決するための手段
本発明は、結晶化可能なガラス・ホーロ材料をいったん
非晶質化した層とし、この非晶質層の表面に導電ペース
ト材料を印刷塗布し、これを上記ガラス・ホーロ材料の
結晶化温度以上で焼成することによって結晶化したガラ
ス・ホーロ層上に導電性回路を形成することを特徴とし
た導電回路の製造方法に関するものである。Means for Solving the Problems The present invention provides a layer of crystallizable glass hollow material that is once made amorphous, a conductive paste material is printed and coated on the surface of this amorphous layer, and this is applied to the above-mentioned glass. - It relates to a method for manufacturing a conductive circuit characterized by forming a conductive circuit on a glass hollow layer crystallized by firing at a temperature higher than the crystallization temperature of the hollow material.
作 用
本発明によれば、結晶化する前段階の非晶質ホーロ層上
に金などの印刷ペースト層を形成し、つづいて非晶質ホ
ーロ層が結晶化する温度で、この非晶質ホーロ層と印刷
ペースト層とを同時に焼成するものであシ、結晶化ホー
ロ層の表面粗度が非常に小さくなり、なおかつ結晶化ホ
ーロ層と導電層との密着強度も大きなものになる。この
結果、従来のように結晶化ホーロ層（表面粗度が０．１
〜０．２．ｘｍ）の上に印刷ペーストを形成し、つづい
て焼成することによってホーロ層上に導電回路を得る従
来方法と比較すると、本発明になる方法では、従来のグ
レーズアルミナ基板なみの表面粗度の平滑なホーロ面の
上に金などの微細な導、電パターンを形成することが可
能になり、例えば、θ本〜１２本／順の微細導電パター
ンが要求され、なおかつ基板の熱伝導に制約が要求され
る、たとえばサーマルヘッド用の基板として大きな効果
を発揮する。According to the present invention, a printing paste layer of gold or the like is formed on the amorphous hollow layer before crystallization, and then the amorphous hollow layer is heated at a temperature at which the amorphous hollow layer crystallizes. Since the layer and the printing paste layer are simultaneously fired, the surface roughness of the crystallized hollow layer becomes extremely small, and the adhesion strength between the crystallized hollow layer and the conductive layer is also increased. As a result, the crystallized hollow layer (surface roughness of 0.1
~0.2. In comparison with the conventional method of forming a printing paste on the hollow layer (xm) and subsequently baking it to obtain a conductive circuit on the hollow layer, the method of the present invention has a surface roughness as smooth as that of a conventional glazed alumina substrate. It is now possible to form fine conductive patterns such as gold on a hollow hollow surface. For example, a fine conductive pattern of θ to 12 conductive patterns is required, and there are also restrictions on heat conduction of the substrate. For example, it is highly effective as a substrate for a thermal head.
実施例
本発明の具体的な実施例を説明する前に本発明の基本的
なプロセスおよび原理について若干の説明を図面に従っ
て行なう。Embodiments Before describing specific embodiments of the present invention, some explanations regarding the basic process and principle of the present invention will be given with reference to the drawings.
第１図は、本発明の導電回路パターンの製造法基材はア
ルミナ基板でこれにガラスフリットを吹付けても良い。FIG. 1 shows a method of manufacturing a conductive circuit pattern according to the present invention.The base material is an alumina substrate, and a glass frit may be sprayed onto this substrate.
つづいてこれを、ガラスフリット層２の材料の結晶化温
度以下の温度でいったん非（り
品質層３とする。この非晶質層の表面に、メタル＾
オルガニック、粉末金属−ガラスフリットなどの（よ）
導電性ペーストを印刷し、ペースト層４を形成し、さら
につづいて上記の非晶質化する温度より高いガラスの結
晶化する温度で非晶質層３．ペースト層４を同時に焼成
する。この結果、第１図ｅに示すように、鋼板１上の結
晶化ホーロ層６と、この層５の上の例えば金のような材
料から成る導電層６が得られる。Next, this is made into an amorphous quality layer 3 at a temperature below the crystallization temperature of the material of the glass frit layer 2. On the surface of this amorphous layer, a layer of metal, organic, powdered metal-glass frit, etc. is applied. (Yo) Print a conductive paste to form a paste layer 4, and then simultaneously fire the amorphous layer 3 and paste layer 4 at a temperature at which the glass crystallizes, which is higher than the temperature at which it becomes amorphous. As a result, as shown in FIG. 1e, a crystallized hollow layer 6 on the steel plate 1 and a conductive layer 6 made of a material such as gold on this layer 5 are obtained.
第６図は、比較のために、ホーロ表面に導電層を得る従
来の製造方法をまとめたものである。鋼板１ｏの表面に
ガラスフリットを電着法などにより付着形成したガラス
フリット層１１とし、これを、ガラスフリットの結晶化
温度以上にまで一挙に昇温し結晶化ガラス・ホーロ層１
２を得、この層１２の表面にメタルオルガニック、金属
粉末−ガラスフリットなどから成る印刷ペーストを塗布
形成し導電性ペースト層１３とし、これを導電性ペース
トの焼成可能な温度（先述の結晶化温度より高い温度）
で焼成し導電体層１４を得る。For comparison, FIG. 6 summarizes conventional manufacturing methods for obtaining a conductive layer on the hollow surface. A glass frit layer 11 is formed by depositing a glass frit on the surface of a steel plate 1o by electrodeposition or the like, and this is heated all at once to a temperature higher than the crystallization temperature of the glass frit to form a crystallized glass hollow layer 1.
2 is obtained, and a printing paste made of metal organic, metal powder-glass frit, etc. is coated on the surface of this layer 12 to form a conductive paste layer 13, and this is heated at a temperature at which the conductive paste can be fired (as described above for crystallization). temperature)
The conductor layer 14 is obtained by firing.
第２図は本発明の詳細な説明するための図であるが、本
発明の方法では、いったん非晶質化したホーロ層２ｏの
表面に導電ペースト２１を形成し、両者が直接界面２２
で接触した状態で、ホーロ層２０の結晶化が進むため、
この間に両者の化学反応、もしくは導電ペーストが接触
していることによりガラスの結晶化時の物理的環境が異
なることによる結晶化条件の制御のいずれかが起こり、
最終的に平滑なホーロ面と、この上の導電層形成が行な
われる。上記化学反応は、メタルオルガニック、金属粉
−ガラスフリットペーストなどの導電ペースト中の構成
成分がホーロの結晶化過程において、ホーロガラス成分
と結晶化過程において何らかの化学反応を起こすことな
どであり、物理的環境の変化とは、結晶化が空気中でオ
ープン状態で行なわれるか、非晶質層上を異物質がおお
っているかの差である。FIG. 2 is a diagram for explaining the present invention in detail. In the method of the present invention, a conductive paste 21 is formed on the surface of the hollow layer 2o, which has once been made amorphous, and both are directly connected to the interface 22.
Because the crystallization of the hollow layer 20 progresses while in contact with the
During this time, either a chemical reaction between the two or a control of crystallization conditions due to a difference in the physical environment during crystallization of the glass due to contact between the conductive pastes occurs.
Finally, a smooth hollow surface and a conductive layer are formed thereon. The above chemical reaction is a chemical reaction that occurs between the constituent components of conductive pastes such as metal organic and metal powder-glass frit pastes and the hollow glass components during the crystallization process of the hollow glass. The change in environment refers to whether crystallization occurs in the open in the air or whether a foreign substance covers the amorphous layer.
本発明で得られた導電層（例えば金メタルオルガニック
を用いて得られた全導電ノー）を化学エツチングして、
金層とホーロ層との界面を見ると、その表面粗度は０．
０２〜０．０８であり、アルミナグレーズのそれとほぼ
同等である。Chemically etching the conductive layer obtained according to the present invention (for example, a fully conductive layer obtained using gold metal organic),
Looking at the interface between the gold layer and the hollow layer, the surface roughness is 0.
02 to 0.08, which is almost equivalent to that of alumina glaze.
次に本発明の具体的な実施例をいくつか述べる。Next, some specific examples of the present invention will be described.
〔実施例１〕
厚さ０．６＋ｏ＋の５ＵＳ４３０基材の表面に電解電着
法により、ガラスフリット層を形成する。このガラスフ
リットの組成は、Ｂａ０１５重量％。[Example 1] A glass frit layer is formed on the surface of a 5US430 substrate with a thickness of 0.6+o+ by electrolytic electrodeposition. The composition of this glass frit is Ba015% by weight.
Ｎ ａ ２０１重量％を含む硼硅酸ガラスである。これ
を７００℃３０分焼成する。得られたホーロ層の上に印
刷法によってＡｕ−メタルオルガニック層を印刷する。It is a borosilicate glass containing 201% by weight Na. This is baked at 700°C for 30 minutes. An Au-metal organic layer is printed on the obtained hollow layer by a printing method.
これを８００ ｔｌ：６分間焼成する。得られたＡｕ導
電層をフォトソノエツチング法を用いて１２本／閣のチ
ドリ状電極にパターン形成し、この電極上にＲｕ Ｏ２
ガラスフリツトから成る抵抗体ペーストを巾１００．ｇ
ｍで印刷塗布、焼成する。This is baked for 800 tl: 6 minutes. The obtained Au conductive layer was patterned into 12 plover-shaped electrodes using a photosonoetching method, and RuO2 was deposited on this electrode.
Resistor paste made of glass frit is 100mm wide. g
Print coating and baking at m.
さらにガラスグレーズオーバーコート層を印刷焼成法に
より形成する。第３図は、本実施例により得られたサー
マルヘッドの断面構成であり、５ＵＳ４３０基材３０．
ホーロ層３１．金電極層３２、Ｒｕ○２ガラスフリット
抵抗層３ｓ、、ｔ−／＜−コートガラスグレーズ層３４
より成る。Furthermore, a glass glaze overcoat layer is formed by a printing and baking method. FIG. 3 shows the cross-sectional structure of the thermal head obtained in this example, showing the 5US430 base material 30.
Hollow layer 31. Gold electrode layer 32, Ru○2 glass frit resistance layer 3s, t-/<- coated glass glaze layer 34
Consists of.
〔実施例２〕
実施例１におけるＡｕ−メタルオルガニックの代わりに
Ａｕ粉末−ガラスフリットペーストｔ−用いて同じくサ
ーマルヘッドを形成した。[Example 2] A thermal head was similarly formed using Au powder-glass frit paste T- instead of the Au-metal organic in Example 1.
〔実施例３〕
アルミナセラミック基板（９９％Ａ１２０３）上に結晶
化可能なガラス材料を吹付は担持し、これを非晶化温度
で焼成しいったん非晶質層とする。この表面にＡｕ−メ
タルオルガニックを印刷し、非晶質ガラスの結晶化温度
まで昇温し、結晶化グレーズとする。得られたＡｕ層は
実施例１と同じ方法で微細パターン化し、つづいて実施
例１と同じくサーマルヘッドを得る。[Example 3] A crystallizable glass material is supported on an alumina ceramic substrate (99% A1203) by spraying, and this is fired at an amorphous temperature to once form an amorphous layer. Au-metal organic is printed on this surface, and the temperature is raised to the crystallization temperature of amorphous glass to form a crystallized glaze. The obtained Au layer is finely patterned in the same manner as in Example 1, and then a thermal head is obtained in the same manner as in Example 1.
〔比較例１〕
厚さ０．６閣の５ＵＳ４３０基材の表面に実施例１と同
じ方法でガラスフリット層を形成する。これを８６０℃
１０間焼成して結晶化ホーロ層を得る。この上にＡｕ−
メタルオルガニックペーストを印刷し８５０℃で焼成し
Ａｕ層を得る。以降は実施例１と同じ方法でサーマルヘ
ッドを形成する。[Comparative Example 1] A glass frit layer was formed on the surface of a 5US430 substrate having a thickness of 0.6 mm using the same method as in Example 1. This is 860℃
A crystallized hollow layer is obtained by firing for 10 minutes. On top of this, Au-
A metal organic paste is printed and fired at 850°C to obtain an Au layer. Thereafter, a thermal head is formed using the same method as in Example 1.
〔比較例２〕−
厚さ０．６順のグレーズアルミナ基板上にＡ ｕ −メ
タルオルガニックを印刷焼成し、実施例１と同じ方法で
サーマルヘッドを得る。[Comparative Example 2] A thermal head is obtained in the same manner as in Example 1 by printing and firing Au-metal organic on a glazed alumina substrate with a thickness of 0.6.
〔実施例４〕
第４図に示すように予めフリッカ３９を入れたアルミナ
基板４ｏの上に結晶化可能なガラス層を非晶質状態で形
成し、この上にＡｑ−メタルオルガニックペーストを電
極パターン印刷し、ガラス層の結晶化温度以上の温度で
これを焼成する。この上にＲｕ Ｏ２−ガラススリット
抵抗を印刷焼成し、さらにガラスオーバーコート層を印
刷焼成により形成し、フリッカ部でカットし、チップ抵
抗とする。４１は電極層、４２は抵抗層、４３はオーバ
ーコート層である。４４は結晶化グレーズ層である。[Example 4] As shown in FIG. 4, a crystallizable glass layer is formed in an amorphous state on an alumina substrate 4o on which a flicker 39 has been inserted in advance, and an Aq-metal organic paste is applied as an electrode on this layer. A pattern is printed and fired at a temperature higher than the crystallization temperature of the glass layer. On top of this, a RuO2-glass slit resistor is printed and fired, and a glass overcoat layer is further formed by printing and fired, and cut at the flicker portion to form a chip resistor. 41 is an electrode layer, 42 is a resistance layer, and 43 is an overcoat layer. 44 is a crystallized glaze layer.
〔比較例３〕
アル、ミナ基板上にＡｑ−ガラスフリットを印刷焼成し
、Ｒｕ Ｏ２−ガラスフリットを印刷焼成し、さらにオ
ーバーコートを印刷焼成し、フリッカ部でカットしチッ
プ抵抗とする。[Comparative Example 3] An Aq-glass frit is printed and fired on an aluminum or mina substrate, a RuO2-glass frit is printed and fired, and an overcoat is further printed and fired, and is cut at the flicker portion to form a chip resistor.
ら−人１０４−（’ｓ）
第１表
発明の効果
以上記載のように本発明によれば、金属基材の上のホー
ロ層や、アルミナ基板の表面の結晶化グレーズ層の表面
粗度を従来の非晶質アルミナグレーズと同等以上の基板
を得ることが可能になり、この平滑な基板の表面に微細
パターン状に導電回路を形成することができる。その結
果、本発明の製造法をサーマルヘッドに応用した場合、
抵抗値ばらつきを小さくでき、電極と抵抗体との接触抵
抗を小さくできサーマルヘッドの長寿命化も可能になる
。104-('s) Table 1 Effects of the Invention As described above, according to the present invention, the surface roughness of the hollow layer on the metal base material and the crystallized glaze layer on the surface of the alumina substrate can be improved. It becomes possible to obtain a substrate that is equivalent to or better than conventional amorphous alumina glaze, and it is possible to form a conductive circuit in a fine pattern on the surface of this smooth substrate. As a result, when the manufacturing method of the present invention is applied to a thermal head,
Variations in resistance values can be reduced, contact resistance between electrodes and resistors can be reduced, and the life of the thermal head can be extended.
サーマルヘッドの場合、基板の蓄熱性が要求され、結晶
化ガラス層は熱伝導性が悪いため、この要求を満足する
が、この熱物性を有したまま表面を平滑にすることが可
能な本発明の方法は、優れた熱効率と抵抗均一性を有す
るサーマルヘッドを提供できることになり、工業的価値
は非常に大なるものである。In the case of a thermal head, the substrate is required to have heat storage properties, and the crystallized glass layer has poor thermal conductivity, so this requirement can be met, but the present invention can make the surface smooth while maintaining this thermal property. This method can provide a thermal head with excellent thermal efficiency and resistance uniformity, and has great industrial value.
第１図は本発明の導電回路の製造プロセスを示す図、第
２図は本発明のガラス・ホーロの結晶化時の様子を示す
模式図、第３図は本発明の方法を用いて得られたサーマ
ルヘッドの一例の断面図７、第４図は本発明の方法を用
いて得られたチップ抵抗器の断面図、第６図は従来のホ
ーロ基板上に導電回路を形成する方法のプロセス図、第
６図および第７図はいずれも従来法によるサーマルヘッ
ドの構成図である。
１・・・・・・鋼板、２・・・・・・ガラスフリット層
、３・・・・・・非晶質層、４・・・・・・ペースト層
、６・・・・・・結晶化ホーロ層、６・・・・・・導電
層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
第３図
第４図
第５図
第６図
第７図Figure 1 is a diagram showing the manufacturing process of the conductive circuit of the present invention, Figure 2 is a schematic diagram showing the state of the glass hollow of the present invention during crystallization, and Figure 3 is a diagram showing the process of manufacturing the conductive circuit of the present invention. 7 is a cross-sectional view of an example of a thermal head obtained using the method of the present invention, and FIG. 4 is a cross-sectional view of a chip resistor obtained using the method of the present invention, and FIG. 6 is a process diagram of a conventional method for forming a conductive circuit on a hollow substrate. , FIG. 6, and FIG. 7 are all configuration diagrams of a conventional thermal head. DESCRIPTION OF SYMBOLS 1... Steel plate, 2... Glass frit layer, 3... Amorphous layer, 4... Paste layer, 6... Crystal Hololayer, 6... Conductive layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7
Claims (6)
成して、一旦非晶質化し、前記非晶質層の表面に導電性
ペースト層を形成した後、前記ガラス・ホーロ材料の結
晶化開始温度以上の温度で焼成して少なくとも一部分結
晶化したガラス・ホーロ層上に導電性回路を形成するこ
とを特徴とする導電回路の製造方法。(1) After forming a crystallizable glass hollow material layer on a substrate and once making it amorphous, forming a conductive paste layer on the surface of the amorphous layer, crystallizing the glass hollow material. 1. A method for producing a conductive circuit, which comprises forming a conductive circuit on a glass hollow layer that is at least partially crystallized by firing at a temperature equal to or higher than the crystallization start temperature.
ホーロ層であることを特徴とする特許請求の範囲第１項
記載の導電回路の製造方法。(2) The method for manufacturing a conductive circuit according to claim 1, wherein the substrate is a hollow layer formed on the surface of a steel plate, stainless steel, or the like.
メルカプチド、カルボン酸塩、アルコキシドのいずれか
を溶媒に溶かしたものであることを特徴とする特許請求
の範囲第１項記載の導電回路の製造方法。(3) The conductive circuit according to claim 1, wherein the conductive paste material is a mercaptide, carboxylate, or alkoxide of Au, Cu, Pt, etc. dissolved in a solvent. manufacturing method.
属粉末とガラスフリットとを主成分としたペースト材料
であることを特徴とする特許請求の範囲第１項記載の導
電回路の製造方法。(4) The method for manufacturing a conductive circuit according to claim 1, wherein the conductive paste material is a paste material mainly composed of metal powder such as Au, Cu, or Pt and glass frit.
土類金属の酸化物（ＢａＯ、ＭｇＯ、ＣａＯ、ＺｎＯ）
のいずれかを１５重量％以上含有し、一価アルカリ金属
の酸化物（Ｎａ＿２Ｏ、Ｋ＿２Ｏ、Ｌｉ＿２Ｏ）を２重
量パーセント以下の組成を有することを特徴とする特許
請求の範囲第１項記載の導電回路の製造方法。(5) The glass hollow material is at least an alkaline earth metal oxide (BaO, MgO, CaO, ZnO)
The conductive circuit according to claim 1, characterized in that it contains 15% by weight or more of any one of the following, and has a composition of 2% by weight or less of monovalent alkali metal oxides (Na_2O, K_2O, Li_2O). manufacturing method.
化ピークを有し、８５０〜９５０℃に第２結晶化ピーク
を有するものであることを特徴とする特許請求の範囲第
４項記載の導電回路の製造方法。(6) Claim 4, characterized in that the hollow material has a first crystallization peak at 700-800°C and a second crystallization peak at 850-950°C. A method for manufacturing a conductive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61252212A JPH0793500B2 (en) | 1986-10-23 | 1986-10-23 | Method of manufacturing conductive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61252212A JPH0793500B2 (en) | 1986-10-23 | 1986-10-23 | Method of manufacturing conductive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63107093A true JPS63107093A (en) | 1988-05-12 |
| JPH0793500B2 JPH0793500B2 (en) | 1995-10-09 |
Family
ID=17234063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61252212A Expired - Fee Related JPH0793500B2 (en) | 1986-10-23 | 1986-10-23 | Method of manufacturing conductive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793500B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02303184A (en) * | 1989-05-18 | 1990-12-17 | Matsushita Electric Ind Co Ltd | Enamelled circuit board and manufacture thereof |
| JPH0386559A (en) * | 1989-08-30 | 1991-04-11 | Matsushita Electric Ind Co Ltd | Thermal head and production thereof |
| JPH0488694A (en) * | 1990-07-31 | 1992-03-23 | Matsushita Electric Ind Co Ltd | Enameled foil substrate, electronic component provided therewith, and manufacture thereof |
| JP2015532533A (en) * | 2012-10-05 | 2015-11-09 | タイコ・エレクトロニクス・コーポレイションＴｙｃｏ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐｏｒａｔｉｏｎ | Electrical component and method and system for manufacturing electrical component |
| JP2016521237A (en) * | 2013-04-10 | 2016-07-21 | ショット グラス テクノロジーズ （スゾウ） カンパニー リミテッドＳｃｈｏｔｔ Ｇｌａｓｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ （Ｓｕｚｈｏｕ） Ｃｏ．， Ｌｔｄ． | Flexible glass / metal foil composite article and method for producing the same |
| WO2019031199A1 (en) * | 2017-08-10 | 2019-02-14 | ローム株式会社 | Thermal print head and thermal print head manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6233836A (en) * | 1985-08-06 | 1987-02-13 | ユニチカ株式会社 | Special interlaced yarn |
-
1986
- 1986-10-23 JP JP61252212A patent/JPH0793500B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6233836A (en) * | 1985-08-06 | 1987-02-13 | ユニチカ株式会社 | Special interlaced yarn |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02303184A (en) * | 1989-05-18 | 1990-12-17 | Matsushita Electric Ind Co Ltd | Enamelled circuit board and manufacture thereof |
| JPH0386559A (en) * | 1989-08-30 | 1991-04-11 | Matsushita Electric Ind Co Ltd | Thermal head and production thereof |
| JPH0488694A (en) * | 1990-07-31 | 1992-03-23 | Matsushita Electric Ind Co Ltd | Enameled foil substrate, electronic component provided therewith, and manufacture thereof |
| JP2015532533A (en) * | 2012-10-05 | 2015-11-09 | タイコ・エレクトロニクス・コーポレイションＴｙｃｏ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐｏｒａｔｉｏｎ | Electrical component and method and system for manufacturing electrical component |
| JP2016521237A (en) * | 2013-04-10 | 2016-07-21 | ショット グラス テクノロジーズ （スゾウ） カンパニー リミテッドＳｃｈｏｔｔ Ｇｌａｓｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ （Ｓｕｚｈｏｕ） Ｃｏ．， Ｌｔｄ． | Flexible glass / metal foil composite article and method for producing the same |
| WO2019031199A1 (en) * | 2017-08-10 | 2019-02-14 | ローム株式会社 | Thermal print head and thermal print head manufacturing method |
| CN111372786A (en) * | 2017-08-10 | 2020-07-03 | 罗姆股份有限公司 | Thermal print head and method of manufacturing thermal print head |
| JPWO2019031199A1 (en) * | 2017-08-10 | 2020-08-13 | ローム株式会社 | Thermal print head and method for manufacturing thermal print head |
| CN111372786B (en) * | 2017-08-10 | 2022-03-25 | 罗姆股份有限公司 | Thermal print head and method of manufacturing thermal print head |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793500B2 (en) | 1995-10-09 |
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