JPS6310459B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus, and particularly to an information processing apparatus that writes or reads diagnostic data, initial setting data, etc. via a shift path.

(Prior Art) As shown in FIG. 1, this type of information processing device has conventionally used a system for converting write data from byte parallel format to bit serial format and converting read data from bit serial format to byte parallel format. A format conversion shift register 10, a shift counter 1 for counting the number of shifts of this format conversion shift register 10, a shift data memory 6 for storing shift data, and a storage address of this shift data memory 6 is specified. It consists of a shift address register 2 for controlling the shift operation, and a shift control circuit 8 for controlling the shift operation, and the unit that is shifted in and out by the shift pass is the package unit.

As shown in Figure 2, memory α is connected to package A.
and package B, and if package A is configured to include the upper byte of memory α and package B includes the lower byte of memory α, diagnostic data, initial setting data, etc. will be written to memory α. At this time, the shift-in data of package A is stored in the format conversion shift register 10 by the firmware, the start address of the shift data memory 6 is set in the shift address register 2, and the number of shifts is set in the shift counter 1. Then, the shift control circuit 8 is activated, and the shift-in data in the package A stored in the format conversion shift register 10 is transferred to the shift data memory 6 and stored therein. When the shift-in data is stored in the shift data memory 6, the firmware stores the shift-in data in the shift data memory 6.
The start address of is set in the shift address register 2, and the shift control circuit 4 is activated. Therefore, for package A, shift data memory 6
Shift-in data is shifted in from. Next, shift-in data is shifted into package B using the same procedure as above. When the shift-in data is shifted in to package A and package B, the firmware supplies write pulses for memory α to package A and package B, and The data that had been shifted into the write registers 102 and 202 is written to the address value that had been shifted into the address register 103 of the memory α in package A.

Here, the firmware changes the data in the write registers 102 and 202 on the shift-in data and the data in the address register 103 on the firmware memory, and uses the above procedure to change the data in the write registers 102 and 202 and the data in the address register 103, and
Write to. Therefore, when writing to a memory divided into a plurality of packages, the firmware stores shift-in data in the shift data memory 6 in units of packages for each address of the memory to be written via the shift path.
Shift in and provide write pulses to the associated packages. At this time, the shift-in data that is changed every time the memory address operation is performed via the shift path is limited to write data and address data, and other shift-in data always remains the same. The firmware must store this same shift-in data as shift-in data in the shift data memory 6 for each memory address to which writing is performed via the shift path. As a result, the burden on the firmware increases, and the execution time for diagnosis, initial settings, etc. becomes significantly longer.

(Object of the Invention) An object of the present invention is to provide a shift path when writing to a memory divided into multiple packages in an information processing device that writes/reads diagnostic information or writes initial setting data via a shift path. In addition to providing an editing data memory separate from the data memory, in order to store shift-in data of multiple packages to the shift data memory, a shift address counter is provided to count the number of updates to the shift address register. Therefore, the basic data related to shift-in data of multiple packages is stored in the shift data memory, and the write data and address of the shift-in data are changed for each memory address written to the editing data memory via the shift path. Shift the write data and address data stored in the editing data memory for each memory address where the data is stored and write via the shift path.The corresponding area of the basic data of the shift-in data of each package on the data memory. It is an object of the present invention to provide an information processing apparatus which solves the above-mentioned drawbacks by storing and shifting in the information processing apparatus, reduces the burden on firmware, and significantly shortens the execution time required for diagnosis, initial setting, etc.

(Structure of the Invention) The information processing device according to the present invention writes and reads diagnostic information via a shift path, and includes a shift data memory, an editing data memory, a shift address register, and a shift address counter. , a format conversion shift register, a shift counter, and a shift control circuit.

The shift data memory is for storing shift data including read/write data.

The editing data memory is for selectively storing editing data from among the shift data.

The shift address register is used to hold the address of the shift data memory and editing data memory currently being executed.

The shift address counter is used to count the number of updates to the shift address register.

The format conversion shift register converts the write data stored in the shift data memory and the editing data memory from the byte parallel format to the bit serial format, and also converts the write data stored in the shift data memory and the editing data memory into the bit serial format. It is used to convert data from bit serial format to byte parallel format.

The shift counter is for counting the number of shifts of the shift register.

The shift control circuit uses the output of the shift address counter to control the shift operation.

(Example) Next, the present invention will be described in detail with reference to the drawings.

In FIG. 3 showing an embodiment of the information processing apparatus according to the present invention, 6 is a shift data memory for storing shift data, 7 is an editing data memory for storing edited data in the shift data, 2 3 is a shift address register for instructing the storage address of the shift data memory 6 and editing data memory 7 during execution; 3 is a shift address counter for counting the number of updates of the shift address register 2; 4 is a shift address counter. 3
5 is a first selection circuit for selecting the contents of the shift data memory 6 or the editing data memory 7;
A format conversion shifter 10 converts the write data stored in the shift data memory 6 and the editing data memory 7 from byte parallel format to bit serial format, and the read data from bit serial format to byte parallel format. Register 9 is a format conversion shift register 10
the second for selecting write data stored in
1 is a shift counter for counting the number of shifts stored in the format conversion shift register 10, and 8 is a shift control circuit for controlling the shift operation.

Writing from firmware to shift counter 1, shift address register 2, shift stop address register 3, and format conversion shift register 10 is performed via bus 20. Reading of data from the format conversion shift register 10 is also performed via the bus 20. The contents of the shift data memory 6 are sent as shift-in data SI to each package. Further, the shift-out data SO from each package is written to the shift data memory 6 via a selection circuit 5 for selecting the contents of the shift data memory 6 or the contents of the editing data memory 7.

When writing to memory α that can be written to via a shift bus that is divided into two packages A and B, the firmware first transfers the shift-in data to the first package A. The basic data regarding the format conversion is stored in the format conversion shift register 10, and the start address of the shift data memory 6 is set in the shift address register 2.
Further, a value obtained by decrementing 1 from the number of bits of the shift-in data in package A is set in the shift address counter 3. Therefore, when the number of shifts is set in the shift counter 1 and the shift control circuit 8 is activated by the firmware, the data in the package A on the format conversion shift register 10 is transferred to the shift data memory 6 via the first selection circuit 5. First part of basic data regarding shift-in data
Store bits. Therefore, the contents of shift counter 1 are decremented by 1, and the contents of shift address register 2 are decremented by 1. Furthermore, the contents of the shift address counter 3 are also decremented by one.
The first selection circuit 5 selects the second bit of the basic data regarding the shift-in data in the package A on the format conversion shift register 10 for the address of the shift data memory 6 specified by the decremented contents of the shift address register 2. Store via . Therefore, the contents of the shift counter 1 and the contents of the shift address register 2 are decremented by 1 again. Further, the contents of the shift address counter 3 are also decremented by one. This operation is repeated until the contents of shift counter 1 become 0 or the contents of shift address counter 3 become 0.

If the contents of the shift counter 1 have reached 0 and the contents of the shift address counter 3 have not yet become 0, all of the shift-in data in the package A has not been stored in the shift data memory 6. Therefore, the firmware stores the remainder of the shift-in data in package A in the format conversion shift register 10 again, sets the number of shifts in the shift counter 1, and activates the shift control circuit 8.

When the contents of the shift address counter 3 become 0, all the basic data regarding the shift-in data in the package A are stored in the shift data memory 6. Next, the firmware stores basic data regarding the shift-in data for the second package B in the shift data memory 6. In this case, shift address register 2
sets the address value next to the address value in which the shift-in data in package A is stored. Shift address counter 3 contains 1 from the number of bits of shift-in data in package B.
Set the value decremented by . Therefore, the number of shifts is set in the shift counter 1, and the shift control circuit 8 is activated in the same way as in package A. When the contents of the shift stop address register 3 and the contents of the shift address register 2 match, it is determined that all the basic data related to the shift-in data in packages A and B have been stored in the shift data memory 6. Become.

Next, in order to write data to the memory α that can be written to via the shift path, the necessary write data, address data, and control data group are included in the shift-in data in package A and package B. is stored in the editing data memory. In this case as well, the shift data memory 6
The basic data regarding the shift-in data in package A and package B is stored using the same procedure as in the case of storing basic data regarding shift-in data for package A and package B. When the write data, address data, and control data group of the memory α that can be written to the editing data memory 7 via the shift path are stored, the write data is then stored from the editing data memory 7. , address data, and control data are transferred to the corresponding areas on shift data memory 6 for basic data regarding shift-in data in package A and package B.

This transfer procedure is performed as follows. First, one address data of the address data group in package A is transferred from the editing data memory 7 to the data area of the address register 103 of package A. The start address of the address data group in package A is set from the editing data memory 7 to the shift address register 2, and a value obtained by decrementing the number of bits of address data in package A by 1 is set in the shift address counter 3. The number of shifts is set for shift counter 1. Therefore,
Shift control circuit 8 is activated. As a result, the format conversion shift register 1 is transferred via the second selection circuit 9.
The first bit of the address data is transferred from the editing data memory 7 to 0. Therefore, the firmware decrements the contents of shift counter 1 by 1, and decrements the contents of shift address register 2 by 1. At this time, shift address counter 3
The contents of are also decremented by 1. The contents of the editing data memory 7 designated by the decremented contents of the shift address register 2 are transferred via the second selection circuit 9 to the format conversion shift register 10 as the second bit of address data. Thereafter, the contents of shift counter 1, shift address register 2, and shift address counter 3 are decremented by 1 again. This operation is repeated until the contents of the shift address counter 3 become 0. When the contents of the shift address counter 3 become 0, it means that one address data of the address data group in the package A has been transferred from the editing data memory 7 to the shift data memory 6.

Using the same procedure, the firmware transfers one write data of the write data group in package A and control data from the editing data memory 7 to the shift data memory 6. Next, one write data and control data of the write data group in package B are transferred from the editing data memory 7 to the shift data memory 6 in the same manner.

When shift-in data for packages A and B are prepared in the shift data memory 6 by the firmware, shift-in is performed for each package. The procedure in this case is performed as follows. First, in order to shift into package A, the start address of the shift-in data in package A is set from the shift data memory 6 to the shift address register 2, and the start address of the shift-in data in package A is set to the shift address counter 3. The value obtained by decrementing the number of bits by 1 is calculated. Then, the shift control circuit 8 is activated and the package A is shifted in. The shift-in operation is performed until the contents of the shift address counter 3 reach 0. Next, package B is shifted in using the same procedure.

When shift-in is started for package A and package B by the firmware, a write pulse is supplied to each package, and package A Data is written from write registers 102 and 202 in package B and package B. In order to write to the next address in memory α that can be written to via the shift path, the next write data in the write data group in package A and the next write data in the address data group are transferred from the editing data memory. Transfers the next address data and the next write data in the write data group in package B to the shift data memory 6, and further shifts these data into packages A and B to supply a write pulse. do.

The write data in the write data group in package A prepared by the editing data memory 7, the address data in the address data group, and the write data in the write data group in package B are all as described above. The data is transferred to the shift data memory 6 according to the procedure. Next, these data are package A and package B.
and is written to the memory α, which can be written via the shift path by supplying a write pulse, whereupon the write operation ends.

By doing this, the firmware prepares a table showing the division state of the memory to be written, stores the basic data of each package in the shift data memory 6 only once, and creates a group of data to be written to the memory for writing. By preparing the address data group and the control data group in the editing data memory 7, it is possible to write to the memory divided into multiple packages, which greatly reduces the burden on the firmware. , the execution time is also significantly reduced.

(Effects of the Invention) As explained above, the present invention is configured by providing an editing data memory and a shift address counter, so that a memory that can be read/written via a shift path is connected to a plurality of packages. Even if the system is divided into multiple packages, the basic data contained in each package only needs to be stored in the shift data memory once, which reduces the burden on firmware and reduces execution time. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional information processing apparatus. FIG. 2 is a system diagram showing the flow of writing data into memories divided into a plurality of packages in the information processing apparatus shown in FIG. FIG. 3 is a block diagram showing an embodiment of the information processing apparatus of FIG. 1 improved according to the present invention. FIG. 4 is a system diagram showing the flow of writing data into memories divided into a plurality of packages in the information processing apparatus shown in FIG. 1...Shift counter, 2...Shift address register, 3...Shift address counter, 4...
... Comparison circuit, 5, 9 ... Selection circuit, 6 ... Shift data memory, 7 ... Editing data memory, 8 ...
...Shift control circuit, 10...Format conversion shift register, 101,201...Control register, 10
2,202...Write register, 103...Address register, 104,204...Read register, 20...Bus.

Claims (1)

[Claims] 1. In an information processing device that writes and reads diagnostic information via a shift path, there is a shift data memory for storing shift data including read/write data, and a shift data memory including the read/write data. an editing data memory for selectively storing editing data;
a shift address register for holding the address currently being executed in the shift data memory and the editing data memory; an address counter for counting the number of updates of the shift address register; and the shift data memory and the editing data memory. The write data stored in the shift data memory and the editing data memory are converted from byte parallel format to bit serial format, and the read data stored in the shift data memory and editing data memory is converted from bit serial format to byte parallel format. a format conversion shift register for converting to
The present invention is characterized by comprising a shift counter for counting the number of shifts of the format conversion shift register, and a shift control circuit for controlling a shift operation using the output of the shift address counter. Information processing device.