JPS59183439A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the load of firmware by storing both the write data and the address data of an editing data memory to the corresponding areas of the basic data of the shift-in data of each package on the data memory for each memory address. CONSTITUTION:The write data stored in a shift data memory 6 and an editing data memory 7 respectively are converted into a bit serial type from a byte parallel type by a type conversion shift register 10. This register 10 also converts the read data stored in both memories 6 and 7 into a byte parallel type from a bit serial type. The shift frequencies of the register 10 are counted by a shift address counter 3, and the shift operation is controlled 8 by the output of the counter 3. Then the basic data of each package is stored in the memory 6 just one time, and a write data group, an address data group and a control data group are prepared at the memory 7. Thus it is possible to perform writing to the memories divided into plural pacakges.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus, and particularly to an information processing apparatus of a type in which diagnostic data, initial setting data, etc. are loaded into or read out via a shift bus.

(Prior Art) Conventionally, this type of information processing device has been used as shown in Fig. 1.
A format conversion shift register 10 for converting write data from byte parallel format to bit serial format and read data from bit serial format to byte parallel format, and a format conversion shift register 10 for counting the number of shifts of this format conversion shift register 10. A shift counter 1, a shift data memory 6 for storing shift data, a shift address register 2 for indicating the storage address of the shift data memory 6, and a shift control circuit 87 for controlling the shift operation. The unit that was shifted in and out by the shift pass was the package unit.

As shown in FIG. 2, if memory α is composed of package A and package B, package A contains the upper byte of memory σ, and package B contains the lower byte of memory α, then the memory When writing diagnostic data, initial setting data, etc. to α, the shift-in data of package A is stored in the format conversion shift register 10 by the firmware, and the start address of the shift data memory 6 is set in the shift address register 2. is,
The number of shifts is set in shift counter 1. Then, the shift control circuit 8 is activated, and the shift-in data in package A stored in the format conversion shift register 10 is transferred to the shift data memory 6 and stored therein. When the shift-in data is stored in the shift data memory 6, the firmware stores the shift data memory 6.
The next m address is set in the shift address register 2, and the shift control circuit 4 is activated. Therefore, shift-in data is shifted into package A from shift data memory 6. Next, the shift-in date is shifted into package B using the same procedure as described above. When the shift-in data is shifted into packages A and B, the firmware provides write pulses for memory α to packages A and B, and writes the write pulses for memory α in packages A and B to each other. The data that had been shifted into the input registers 102 and 202 is inserted into the address value that had been shifted into the address register 103 of the memory α in package A.

Here, the firmware changes the data in the write registers 102 and 202 and the data in the address register 103 on the shift-in data on the firmware memory,
Writing to the memory α is performed by the above procedure. Therefore, when writing to a memory divided into multiple packages, the firmware stores shift-in data for each package in the shift data memory 6 for each address of the memory to be written to via a shift path, and then shifts it in to the related packages. Provides a write pulse to. At this time, the shift-in data that is changed every time the memory address operation is performed via the shift path is limited to write data and address data, and other shift-in data always remains the same. The firmware must store this same shift-in data as shift-in data in the shift data memory 6 for each memory address to which writing is performed via the shift path. This increases the burden on the firmware and has the disadvantage that the execution time for diagnostics, initial settings, etc. becomes significantly longer.

(Object of the Invention) The purpose of the present invention is to provide a shift path when writing to memory divided into multiple packages in an information processing device that writes/reads diagnostic information or writes initial setting data via a shift path. In addition to providing an editing data memory separate from the data memory, in order to store shift-in data of multiple packages in the shift data memory, a shift address counter is provided to count the number of updates of the shift address register. Basic data related to the shift-in data of multiple packages is stored in the shift data memory, and the write data and address data of the shift-in data are changed for each memory address written to the editing data memory via the shift path. The write data and address data stored in the editing data memory for each memory address to which writing is performed via the shift path are stored in the corresponding area of the basic data of the shift-in data of each package on the shift data memory. It is an object of the present invention to provide an information processing apparatus that solves the above-mentioned drawbacks by shifting in the information processing apparatus, reduces the burden on firmware, and significantly shortens the execution time required for diagnosis, initial setting, and the like.

(Structure of the Invention) An information processing device according to the present invention writes and reads diagnostic information via a shift bus, and! 1', a shifter memory, a data memory for 1 editing, a shift address register, a shift address counter, a format conversion shift register, a shift counter, and a shift control circuit.

The shift data memory is for storing shift data including read/write data.

The editing data memory is for selectively storing editing data from among the shift data.

The shift address register is used to hold the address of the shift data memory and editing data memory currently being executed.

The shift address counter is for counting the number of updates of the shift address register.

The format conversion shift register converts the write data stored in the shift data memory and the editing data memory from the byte parallel format to the bit serial format, and also converts the write data stored in the shift data memory and the editing data memory into the bit serial format. It is used to convert data from bit serial format to byte parallel format.

A shift counter is used to count the number of shifts in the shift register.

The shift control Ml11 circuit uses the output of the shift address counter to control the shift operation.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 3 showing an embodiment of the information processing apparatus according to the present invention, there are shown a shift data memory 61-1' for storing shift data, an editing data memory 71d for storing edited data among the shift data, 2 is a shift address register for indicating the storage address of the shift data memory 6 and the editing data memory 7 during execution; 3 is a shift address counter for counting the number of updates of the shift address register 2; 4t/'i A comparison circuit for detecting 0 of the shift address counter 3, 5 is the contents of the shift data memory 6 or the editing data memory 7
A first selection circuit 10 selects the contents of the shift data memory 6 and editing data memory 7 from the byte parallel format to the bit serial format, and also converts the read data from the byte parallel format to the bit serial format. a format conversion shift register for converting from a serial format to a byte parallel format; 9 a second selection circuit for selecting write data stored in the format conversion shift register 10; 1 a second selection circuit for selecting write data stored in the format conversion shift register 10; Shift counter for counting the number of shifts performed, 8
is a shift control circuit for controlling the shift operation.

Shift counter 1, shift address register 2, and shift stop address register 3.

Writing from the firmware to the format conversion shift data/) 10 is performed via the bus 20. Reading of data from the format conversion shift register 10 is also carried out via the bus 20.
It is done via. The contents of the shift data memory 6 are sent as shift-in data SI to each package. Shift out data S from each package
O is written into the shift data memory 6 via the selection circuit 5 which selects the contents of the shift gator memory 6 or the editing data memory 7.

For memory α, which can be written to via a shift bus that is divided into two packages A and B, [2] When performing evening programming, first shift in firmware H14'l to package A. Basic data regarding data is stored in the format conversion shift register 10, and the start address of the shift data memory 6 is set in the shift address register 2.

Further, a value obtained by subtracting 1 from the number of bits of shift-in data in package A is set in the shift address counter 3. Therefore, when the number of shifts is set in the shift counter 1 and the shift control circuit 8 is activated by the firmware, the package A on the format conversion shift register 10 is transferred to the shift data memory 6 via the first selection circuit 5.
Stores the first 1 bit of basic data related to shift-in data. Therefore, the contents of shift counter 1 are decremented by 1, and the contents of shift address register 2 are decremented by 1. Furthermore, the contents of the shift address counter 3 are also decremented by one.

The first selection circuit 5 selects the second bit of the basic data regarding the shift-in data in the package AK on the format conversion shift register 10 for the address of the shift data memory 6 specified by the decremented contents of the shift address register 2. Store via . Therefore, the contents of the shift counter 1 and the contents of the shift address register 2 are decremented by 1 again. Further, the contents of the shift address counter 3 are also decremented by one. Shift counter 1
This is repeated until the contents of the shift address counter 3 become 01 or the contents of the shift address counter 3 become O.

If the contents of shift counter 1 have reached 0 and the contents of shift address counter 3 have not yet reached 0, all of the shift-in data in package A has not been stored in shift data memory 6. Therefore, the firmware stores the shift-in data in the node cage A again in the format conversion shift register 10, sets the number of shifts in the shift counter 1, and activates the shift control circuit 8.

When the contents of the shift address counter 3 become 0, all basic data related to shift-in data in package A are stored in the shift data memory 6. Next, the basic data regarding the shift-in data in the package B of the firmware Vi 2 pieces is stored in the shift data memory 6. In this case, the shift address register 2 is set with the address value next to the address value in which the shift-in data in package A is stored. The shift address counter 3 is set to a value that is decremented by 1 from the number of pits of the shift-in data in the node cage B. Therefore, the number of shifts is set in the shift counter 1, and the shift control circuit 8 is activated in the same way as in the lock cage A. Shift stop address register 3
When the contents of the shift address register 2 and the contents of the shift address register 2 match, the shift data memory 6 is
This means that all the basic data regarding the shift-in data in Nonotsu cage B has been stored.

Next, in order to write data to memory α, which can be written via the shift path,
The necessary write data, address data, and control data group among the shift-in data for package B and package B are stored in the editing data memo 1. Also in this case,
The basic data regarding the shift-in data for packages A and B is stored in the shift data memory 6 using the same procedure as in the case of storing the basic data regarding the shift-in data for packages A and B. Once the write data, address data, and control data group of the memory α that can be written to the editing data memory I via the shift node are stored, the data is then written from this editing data memory T. data, address data, control data, and -b=transferred to the corresponding area i of the storage area i for basic data related to shift-in data in package A and nut cage B on shift data memory 6.

This transfer procedure is performed as follows. First, one address data of the address data group in package A is transferred to the data area of the address register 103 of package A for editing. The start address of the address data group in blockage A is set, and the address f which is decremented by 1 from the number of bits of address data in blockage A (set in shift address counter 3, The number of shifts is set for counter 1. Then,
Shift control circuit 8 is activated. As a result, the first bit of the address data is transferred from the editing data memory 7 to the format conversion shift register 10 via the second selection circuit 9. Therefore, the firmware decrements the contents of shift counter 1 by 1, and decrements the contents of shift address register 2 by 1. At this time, the contents of the shift address counter 3 are also decremented by . The contents of the editing data memory 7 designated by the decremented contents of the shift address register 2 are transferred via the second selection circuit 9 to the format conversion shift register 10 as the second bit of address data. Thereafter, the contents of shift counter 1, shift address register 2, and shift address counter 3 are decremented by 1 again. This operation is repeated until the contents of the shift address counter 3 reach 0. When the content of the shift address counter 3 becomes O, this means that one address data of the address data group in the package A has been transferred from the editing data memory T to the shift data memory 6.

Using the same procedure, the shift armware transfers one write data and control data of the write data group in package A from the editing data memory 7 to the shift data memory 6. Next, one write data and control data of the write data group in package B are transferred from the editing data memory 7 to the shift data memory 6 in the same manner.

When shift-in data for packages A and B are prepared in the shift data memory 6 by the firmware, shift-in is performed for each package. The procedure in this case is performed as follows. First, in order to shift in to package A, the start address of shift-in data coming from shift data memory 6 to package A is set in shift address register 2, and package A is
The value obtained by decrementing the number of bits of shift-in data by 1 is calculated. Then, the shift control circuit 8 is activated and the package A is shifted in. The shift-in operation is performed until the contents of the shift address counter 3 reach 0. Next, the shift-in is performed for the vehicle B by the same procedure.

When the firmware starts shifting in packages A and B, a write pulse is supplied to each package, and the memory α, which can be written to via the shift path, is Write register 102 in package A and package B
, 202, the data is written. In order to write to the next address of memory α that can be written via the shift path, the next write data in the write data group in package A and the next write data in the address data group are sent from the editing data memory. The following address data and
The next write data in the write data group in package B is transferred to the shift data memory 6, and further,
These data are shifted into packages A and B to provide write pulses.

All of the write data in the write data group in package A, the address data in the address data group, and the write data in the write data group in package B prepared in the editing data memory 7 are as follows. The data is transferred to the shift data memory 6 through the above procedure. These data are then shifted in for packages A and B and written to memory α, which can be written to via the shift path by supplying write pulses, where the write operation is performed. Participate.

By doing this, the firmware prepares a table showing the division state of the memory to be written to, stores the basic data of each package in the shift data memory 6 only once, and stores the data to be written to the memory for writing. with a group,
Address data group.

By preparing the control data group in the editing data memory 7, it is possible to write to the memory divided into multiple packages, which greatly reduces the burden on the firmware and the execution time. That's why.

(Effects of the Invention) As described above, the present invention includes a plurality of packages in which a memory that can be read/written via a shift path is configured by providing an editing data memory and a shift address counter. Even if it is divided into
The basic data included in each package only needs to be stored in the shift data memory once, which has the effect of reducing the burden on the firmware and shortening the execution time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional information processing apparatus. FIG. 2 is a system diagram showing the flow of writing data into memories divided into a plurality of packages in the information processing apparatus shown in FIG. FIG. 3 is a block diagram showing an embodiment of the information processing apparatus of FIG. 1 improved according to the present invention. FIG. 4 is a system diagram showing the flow of writing data into memories divided into a plurality of packages in the information processing apparatus shown in FIG. 1... Shift counter 2...-shift) 7 Dress register 3 @ II 11 Shift address counter 4... Comparison circuit 5.9... Selection circuit 6... Shift data memory 7... Editing data Memory B...Shift control circuit 10...Format conversion shift register 101.201---Control register 102.202・ψ・Write register 103---Address register 104.204...Read register 201111a Bus patent Applicant NEC Corporation Representative Patent Attorney Hisashi Inoro

Claims (1)

[Claims] In an information processing device that writes and reads diagnostic information via a shift path, there is a shift data memory for storing shift data including read/write data, and editing from among the shift data including the read/write data. an editing data memory for selectively storing data; a shift address register for holding the address currently being executed in the shift data memory, the editing data memory, and K; and updating of the shift address register. An address counter for counting the number of times,
Converting the write data stored in the shift data memory and the editing data memory from a byte parallel format to a bit serial format, and further converting the read data stored in the shift data memory and the editing data memory. a format conversion shift register for converting from a bit serial format to a byte parallel format; a shift counter for counting the number of shifts in the format conversion shift register; and control of shift operations using the output of the shift address counter. An information processing device comprising: a shift control circuit for performing the following steps.