JPS6246022B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an information processing apparatus, and particularly to an information processing apparatus that performs diagnosis, writing of initial setting data, etc. using a shift path.

[Prior art]

Conventionally, this type of information processing device has a shift register 7 that converts write data from byte parallel to bit serial and read data from bit serial to byte parallel, as shown in FIG. It consists of a shift counter 1 that counts the number of shifts, a shift data memory 5 that stores shift data, a shift address register 2 that indicates the storage address of the shift data memory 5, and a shift control circuit 8 that controls the shift operation. The unit that is shifted in and out by the shift pass is the package unit.

As shown in FIG. 2, if register REGα is composed of a shift data section of package A, a shift data section, and a shift data section of package B, readout of register REGα is performed by shifting out shift data of package A. When the shift data of package A is stored in the memory 5, the firmware sets the start address of the shift data part in the shift data memory 5 to the shift address register 2, and sets the number of bits of the part to the shift counter 1. , shift control circuit 8
and transfers the data to the shift register 7. The firmware transfers the data stored in the shift register 7 to the firmware memory. Next, the start address of the shift data section is set in the shift address register 2, the number of bits of the section is set in the shift counter 1, the shift control circuit 8 is activated, and the data of the section is transferred to the shift register 7. The firmware transfers the part data stored in the shift register 7 to the firmware memory in the same way as the part.

Next, when the shift data of package B is stored in the shift data memory 5 due to the shift out of package B, the firmware sets the start address of the shift data section on the shift data memory 5 in the shift address register 2, and The number of bits is set in the shift counter 1, the shift control circuit 8 is activated, and the data of the part is transferred to the shift register 7. The firmware transfers the data stored in the shift register 7 to the firmware memory. The data section, section, section, stored on the firmware memory is edited by the firmware and displayed as a register REGα.

Therefore, when reading a register divided into a plurality of packages, the data is shifted out in units of packages, and the necessary shift data portion is stored in the firmware memory by the firmware. After all related packages have been shifted out and the necessary shift data has been stored in the firmware memory, the firmware must edit the shift data in the firmware memory. This has resulted in a disadvantage that the burden on the firmware increases.

[Purpose of the invention]

An object of the present invention is to write and read diagnostic information, write initial setting data, etc. using a shift pass in an information processing device, when writing and reading registers divided into a plurality of packages.
To provide a device in which an editing data memory is provided separately from a shift data memory, and storage of write data, storage of read data, and editing are performed on the editing data memory, thereby reducing the load on firmware and solving the above drawbacks. There is a particular thing.

[Structure of the invention]

The present invention provides an information processing apparatus that writes diagnostic information and reads diagnostic information using a shift pass.
a shift data memory for storing shift data;
an editing data memory that stores edited data of shift data; a shift address register that indicates the storage addresses of the shift data memory and editing data memory; and write data of the shift data memory and editing data memory, from byte parallel to bit parallel. A shift register that converts the read data of the shift data memory and the editing data memory from bit serial to byte parallel; a shift counter that counts the number of shifts in the shift register; and a shift counter that controls the shift operation. The shift control circuit is configured to include a shift control circuit.

[Explanation of Examples]

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 3 showing an embodiment of the present invention, 5 is a shift data memory for storing shift data;
2 is a shift address register indicating the storage address of the shift data memory 5 and the editing data memory 4; 3 is the data stored in the shift data memory 5 and the editing data memory 4; Select the selection circuit,
A shift register 7 converts the write data in the shift data memory 5 and the editing data memory 4 from byte parallel to bit serial, and converts the read data from bit serial to byte parallel;
is the write data selection circuit of the shift register 7,
1 is a shift counter that counts the number of shifts in the shift register 7, and 8 is a shift control circuit that controls the shift operation. Further, writing from the firmware to the shift counter 1, shift address register 2, and shift register 7 is performed via a path. Reading from the firmware of the shift register 7 is also performed via the path.
The output of the shift data memory 5 is sent out as shift-in data SI to each package. Further, the shift-out data SO from each package is written into the shift data memory 5 via the shift data memory 5 and the selection circuit 3 of the editing data memory 4.

First, the register is divided into two packages.
When reading REGα, when the first package A is shifted out, the shift-out data is stored in the shift data memory 5. The shift-out data of package A stored in the shift data memory 5 includes data constituting the register REGα. In order to edit the register REGα on the editing data memory 4, the data is transferred to the editing data memory 4. In the transfer procedure, the start address where the data on the shift data memory 5 is stored is set in the shift address register 2. Next, the number of data bits is set in the shift counter 1, and when the shift control circuit 8 is activated by the firmware, the first bit of the data is transferred from the shift data memory 5 to the shift register 7 via the selection circuit 6. Transport. Then, shift counter 1 is incremented by -1 and shift address register 2 is incremented by -1. The next 1 bit of the data specified by the shift address register 2 that has been set to -1 is transferred to the shift register 7 via the selection circuit 6. Then, shift counter 1 and shift address 2 are incremented by 1 again. This operation is repeated until shift counter 1 becomes "0".

Since the shift counter 1 has become "0", all bits of data have been transferred to the shift register 7. Next, the editing data memory 4 is used to edit the data stored in the shift register 7.
Transfer to. The start address of the editing data memory 4 for storing data in the shift address register 2 is set. When the number of data bits is set in the shift counter 1 and the shift control circuit 8 is activated by the firmware, the first bit of the data stored in the shift register 7 is specified by the shift address register 2 via the selection circuit 3. The edited data is written to the storage address of the editing data memory 4. Then, the shift counter 1 and shift address register 2 are incremented by 1, and the next bit of data is written into the editing data memory 4. This operation is repeated until shift counter 1 reaches "0".

When shift counter 1 becomes “0”,
This means that all bits of data have been transferred to the editing data memory 4. Next, the data is transferred to the editing data memory 4 using the same procedure as described above. At this time, the storage address of the data memory 4 for data editing is set in the register as shown in FIG.
Considering the data structure of REGα, the address must ensure a storage area for the data on package B that will be shifted out next.

Next, package B is shifted out, and the data is transferred to the editing data memory 4 in the same procedure as the data of package A. At this time, the storage address of the editing data memory 4 is between the data as described above. This means that the data in the register REGα can be edited on the editing data memory 4.

The firmware transfers the data on the editing data memory 4 to the shift register 7, and reads out the shift register 7, thereby completing the editing process.

Next, to explain writing to register REGα, the data to be written to register REGα, ,
is stored in the shift register 7, the start address of the editing data memory 4 for storing data, , is set in the shift address register 2, the number of bits of the register REGα is set in the shift counter 1, and the shift control circuit 8 is activated. let The shift control circuit 8 receives the data in the shift register 7,
is stored bit by bit at the address specified by the shift address register 2 of the editing data memory 4. When shift counter 1 becomes "0", all bits of data , are transferred to shift register 7.
This means that the data has been transferred from the editing data memory 4 to the editing data memory 4, and the process ends.

Next, the package A is shifted out and the shift data is stored in the shift data memory 5. The start address of the editing data memory 4 whose data is stored in the shift address register 2 is set. The number of bits of data is set in the shift counter 1, the shift control circuit 8 is activated, and the data is transferred to the shift register 7. The data stored in the shift register 7 is transferred to the area defined in the shift-out data register REGα of package A stored in the shift data memory 5. The transfer procedure sets the start address of the shift data memory 5 for storing data in the shift register 2, sets the number of bits of data in the shift counter 1, and activates the shift control circuit 8. When the shift counter 1 becomes "0", the data is transferred to the shift data memory 5, and the process ends. Next, the data is transferred to the shift data memory 5 in the same procedure as the data. When the data is stored in the shift data memory 5, the firmware shifts the data in the shift data memory 5 into the package A. Next, package B is shifted out, and the data on the editing data memory 4 is transferred to the area of the shift-out data register REGα of package B on the shift data memory 5 in the same manner as the data described above. Next, the data in the shift data memory 5 is shifted into the package B, thereby completing the writing of the register REGα.

In this way, the firmware can write to and read from registers divided into multiple packages by simply preparing a table indicating the division status of the registers to be written to and read from, which greatly reduces the burden on the firmware. becomes less.

〔Effect of the invention〕

As explained above, by providing the editing data memory in the present invention, even if the registers to be read and written by the shift pass are divided into multiple packages, editing can be performed on the editing data memory. This has the effect of reducing the burden.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional information processing device. FIG. 2 is a diagram showing editing of shift data in a conventional information processing device. FIG. 3 is a block diagram showing one embodiment of the present invention. FIG. 4 is a diagram showing editing of shift data in the embodiment of FIG. 3. 1... Shift counter, 2... Shift address register, 3... Selector, 4... Editing data memory, 5... Shift data memory, 6... Selector, 7... Shift register, 8... Shift control circuit .

Claims (1)

[Claims] 1. In an information processing device that writes diagnostic information and reads diagnostic information using a shift pass, a shift data memory that stores shift data, an editing data memory that stores edited data of the shift data, and a shift data memory and the edited a shift address register indicating the storage address of the data memory for editing, converting the write data of the shift data memory and the editing data memory from byte parallel to bit serial, and converting the read data of the shift data memory and the editing data memory into bit serial data. An information processing device comprising: a shift register that converts from serial to byte parallel; a shift counter that counts the number of shifts in the shift register; and a shift control circuit that controls shift operations.