JPS5938858A - Information processing device - Google Patents

Abstract

PURPOSE:To execute editing on an editing data memory even if a register for executing read-out and write by a shift bus is divided into plural packages, by providing the editing data memory. CONSTITUTION:A shift data memory 5 stores a shift data, and an editing data memory 4 stores an editing data of the shift data. A shift address register 2 stores a store address of the shift data memory 5 and the editing data memory 4. A stored data of the shift data memory 5 and the editing data memory 4 is selected by a selecting circuit 3, and is subjected to parallel-serial conversion by a shift register 7. A write data to the shift register 7 is selected by a selecting circuit 6. An output of the shift data memory 5 is supplied as a shift-in data SI to each package, and a shift-out data SO from each package is written in the shift data memory 5 through the selecting circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an information processing device that performs diagnosis, writes initial setting data, and the like.

[Prior art]

Conventionally, this type of information processing device has a shift register 7 that converts write data from byte parallel to bit serial and read data from bit serial to byte parallel, as shown in FIG. A shift counter 1 that counts the number of shifts, a shift data memory 5 that stores shift data, a shift address register 2 that indicates the storage address of the shift data memory 5, and a shift control circuit 8 that controls the shift operation. The unit that is shifted in and out according to the shift pass is a package unit.

As shown in FIG. 2, if the register REGα is composed of the 0th part of the shift data of package A, the 0th part of the shift data, and the 0th part of the shift data of package B, reading of the register BEGα is the shift out of the package A. When the shift data of package A is stored in the shift data memory 5 by The shift counter 1 is set, the shift control circuit 8 is activated, and the 0 part data is transferred to the shift register 7. The 7 armware transfers the 0 part data stored in the shift register 7 to the firmware memory. Next, the start address of the 0th part of the shift data is set in the shift address register 2, the number of bits in the 0th part is set in the shift counter 1, the shift control circuit 8 is activated, and the 0th part data is transferred to the shift register 7. The firmware transfers the 0th copy of data stored in the shift register 7 to the firmware memory in the same manner as the 0th copy.

Next, when the shift data of package B is stored in the shift data memory 5 by shifting out package B, the firmware sets the start address of the 0 part of the shift data on the shift data memory 5 in the shift address register 2, The number of bits in the 0 part is set in the shift counter 1, the shift control circuit 8 is activated, and the data in the 0 part is transferred to the shift register 7. The firmware transfers the 0th copy of data stored in the shift register 7 to the firmware memory. Data stored on firmware memory 20
copy, 0 copy, and 0 copy are edited by firmware and displayed as register BEGα.

Therefore, when reading a register divided into a plurality of packages, the data is shifted out in units of packages, and the necessary shift data portion is stored in the υ firmware memory by the firmware.

After all related packages have been shifted out and the necessary shift data has been stored on the firmware memory, the firmware must edit the shift data on the firmware memory. For this reason, there is a drawback that the burden on the firmware increases.

[Purpose of the invention]

An object of the present invention is to write and read registers divided into a plurality of packages in an information processing device that writes and reads diagnostic information, writes initial setting data, etc. using a shift pass, and edits the registers separately from the shift data memory. An object of the present invention is to provide an apparatus which solves the above-mentioned drawbacks by reducing the burden on firmware by providing a data memory for data collection, and performing storage of write data, storage and editing of read data on the data memory for data collection.

[Structure of the invention]

The present invention provides an information processing apparatus that writes diagnostic information and reads diagnostic information according to a shift path, which includes a shift data memory that stores shift data, an editing data memory that stores edited data of the shift data, and a shift data memory that stores shift data. A shift address register indicating the storage address of the memory and the editing data memory, and the shift data memory and the editing data 5- The write data of the memory is converted from byte parallel to bit serial, and the data is transferred to the shift data memory and the editing data. The device includes a shift register that converts memory read data from bit serial to byte parallel, a shift counter that counts the number of shifts in the shift register, and a shift control circuit that controls the shift operation.

[Explanation of Examples]

Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 3 showing an embodiment of the present invention, 5 is a shift data memory for storing shift data, 4 is an editing data memory for storing edited data of shift data, and 2 is a shift data memory 5 and an editing data memory. 4 is a shift address register indicating the storage address; 3 is a selection circuit for selecting the data to be stored in the shift data memory 5 and the editing data memory 4; and 7 is a selection circuit for selecting the data to be stored in the shift data memory 5 and the editing data memory 4 from byte parallel. A shift register converts read data from bit serial to 6-byte parallel; 6 is a selection circuit for write data of shift register 7; 1 is a shift counter that counts the number of shifts in shift register 7; 8;
This is a shift control circuit that controls the shift operation. Also, writing from the firmware to the shift counter 1, shift address register 2, and shift register 7 is performed via a path at t7. Reading from the firmware of the shift register 7 is also performed via the path. The output of the shift data memory 5 is sent out as shift-in data SI to each package. Further, the shift-out data SO from each package is written to the shift data memory 5 via the shift data memory 5 and the selection circuit 3 of the editing data memory 4.

First, the register REGα is divided into two packages.
When reading out the first package, the shift-out data is stored in the shift data memory 5 when the first package is shifted out. The shift-out data of package A stored in the shift data memory 5 includes register R.
Data ■ and data ■ that constitute EGα are included.

In order to edit the register REGα on the editing data memory 4, data ■ and data ■ are transferred to the editing data memory 4. In the transfer procedure, the shift address register 2 is set to the start address where the data (2) on the shift data memory 5 is stored. Next, the number of bits of the data ■ is set in the shift counter 1, and when the shift control circuit 8 is activated by the firmware, the first bit of the data ■ is transferred from the shift data memory 5 to the shift register 7 via the selection circuit 6. to be transferred. and shift counter 1 to 1
, the shift address register 2 is decremented by -1. The next 1 bit of the data specified by the shift address register 2 that has been set to -1 is sent to the shift register 7 via the selection circuit 6.
will be transferred to. Then, shift counter 1 and shift address register 2 are incremented by 1 again. This operation is repeated until the shift counter 1 reaches 10.

The shift counter 1 becomes 1 ON, so the shift counter 1 turns on.
This means that all bits of are transferred to the shift register 7. Next, the data (2) stored in the shift register 7 is transferred to the editing data memory 4 for editing. Editing data memory 4 that stores data ■ in shift address register 2
Set the start address of. When the number of bits of the data ■ is set in the shift counter 1 and the shift control circuit 8 is activated by the firmware, the first bit of the data ■ stored in the shift register 7 is transferred to the shift address register 2 via the selection circuit 3. It is written to the specified storage address of the editing data memory 4. Then, the shift out 11 causes the shift address register 2 to be incremented by 1, and the next bit of the data ■ is written into the editing data memory 4. Repeat this operation until shift counter 1 reaches 101.
return.

When shift counter 1 becomes NOI, data ■
This means that all bits have been transferred to the editing data memory 4. Next, data (2) is transferred to the editing data memory 4 using the same procedure as data (2).

9- In the case of 17, the storage address of the data memory 4 for editing the data ■ takes into consideration the data structure of the register REGα as shown in Figure 4.17 The storage area for the data ■ on the package B to be shifted out next is secured. It has to be an address.

Next, package B is shifted out, and data ■ is transferred to the editing data memory 4 in the same procedure as data ■ and data ■ of package A. At this time, the storage address of the editing data memory 4 is between the data (2) and the data (2) as described above. As a result, register aE on editing data memory 4 is
This means that the Gα data has been edited.

The firmware transfers the ≠-data ■■■ of the editing data memory 4-hi to the shift register 7, and reads the shift register 7.
This means that the editing process has ended.

Next, to explain the writing to the register REGα, the data ■■■ to be written to the register RBGα is stored in the shift register 7, and the data ■■■ is stored in the shift address register 2 at the 10-start address of the editing data memory 4. and set the number of pits of register REGα in shift counter 1 t71, shift control circuit 8
Activate. The shift control circuit 8 stores the data ■■■ in the shift register 7 bit by bit at the address designated by the shift address register 2 of the editing data memory 4. When the shift counter 1 becomes -Ol, all bits of the υ data ■■■ have been transferred from the shift register 7 to the editing data memory 4, and the process ends.

Next, the package A is shifted out and the shift data is stored in the shift data memory 5. The start address of the vertical multiplication data memory 4 in which the data ■ is stored is set in the shift address register 2.

The number of pits of the data ■ is set in the shift counter 1, the shift control circuit 8 is activated, and the data ■ is transferred to the shift register 7. The data (2) stored in the shift register 7 is transferred to the area defined in the shift-out data register BEGα of package A stored in the shift data memory 5. In the transfer procedure, the start address of the shift data memory 5 that stores the data (2) is set in the shift register 2, the number of pits of the data (2) is set in the shift counter 1, and the shift control circuit 8 is activated.

When the shift counter l becomes %Q#, the data @
has been transferred to the shift data memory 5, and the process ends. Next, the data ■ is transferred to the shift data memory 5 in the same procedure as the data @. When the data ■■ is stored in the shift data memory 5, the firmware shifts the data in the shift data memory 5 into the package A. Next, package B is shifted out, and data (2) on the editing data memory 4 is transferred to the area of the shift-out data register REGα of package B on the shift data memory 5 in the same manner as the data (2) described above.

Next, the data in the shift data memory 5 is shifted into the package B, thereby completing the writing of the register EGα.

In this way, the firmware can write to registers divided into multiple packages by simply preparing a table that shows all the division states of registers that are not subject to writing or reading.
It becomes possible to perform reading, and the burden on the firmware is significantly reduced.

〔Effect of the invention〕

As explained above, by providing an editing data memory in the present invention, even if registers that are read and written by shift passes are divided into multiple packages, editing can be performed on the editing data memory.l Firmware This has the effect of reducing the burden on people.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional information processing device. FIG. 2 is a diagram showing editing of shift data in a conventional information processing device. FIG. 3 is a block diagram showing one embodiment of the present invention. FIG. 4 is a diagram showing editing of shift data in the embodiment of FIG. 3. 1...Shift counter, 2...Shift address register, 3...Selector, 4...
...Editing data memory, 5...Shift data memory, 6...Selector 13-lid, 7...Shift register, 8...
Shift control circuit. 14- US SX Figure 3 Figure 4

Claims (1)

[Claims] In an information processing device that writes diagnostic information and reads diagnostic information on a shift path, a shift data memory that stores shift data, an editing data memory that stores edited data of the shift data, and the shift data memory and the a shift address register indicating a storage address of the editing data memory; converting the write data of the shift data memory and the editing data memory from byte parallel to bit serial; and converting the read data of the shift data memory and the editing data memory; An information processing device comprising: a shift register that converts from bit serial to byte parallel; a shift counter that counts the number of shifts in the shift register; and a shift control circuit that controls shift operations.