JPS6223339B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus monitoring device for monitoring signals on a bus line of a data processing device.

Conventionally, this type of bus monitoring device connects a plurality of probes one by one to the bus line of a corresponding data processing device to input signals on the bus line. However, data processing devices generally have a large number of bus lines, and there is a drawback in that it takes a lot of time to connect the probes of the bus monitoring device to these bus lines. In addition, the connection point where the probe can be connected to the bus line (for example, a wrapping post on a printed circuit board to which the bus line is wired) is located deep inside the data processing device's housing, and it is difficult to identify the connection point by looking at it. In cases where it is difficult to manually connect the probe to the bus line, it takes a particularly long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus monitoring device that overcomes the above-mentioned drawbacks.

The bus monitoring device of the present invention includes a trigger generation means for generating a trigger signal when a signal on a bus line of a data processing device matches a preset pattern and when receiving a signal from the outside; storage means that reads and stores the information and stops reading when the trigger signal is received; a continuation means that reads out the stored contents of the storage means;
A bus monitoring device comprising: a connection portion having the same connection form as a connection portion of the data processing device connected to the bus line.

Next, the present invention will be explained with reference to the drawings.
FIG. 1 is a block diagram showing a data processing device to which an embodiment of the present invention is connected.

The central processing unit 20, the peripheral control units 30, 50, and the main memory 70 are connected to the common bus line 10,
The peripheral devices 40 and 60 are controlled by peripheral control units 30 and 50. Central processing unit 20, peripheral control unit 3
0, 50 and the storage device 70, data is transferred via the common bus line 10 and some processing is performed. On the other hand, the bus monitoring device 80 collects all or part of the bus signals of the common bus line 10 consisting of a plurality of lines during data transfer, that is, when the common bus line 10 becomes active. A peripheral device 90 is connected to the bus monitoring device 80 .

FIG. 2 is a block diagram showing in detail the bus monitoring device 80 to which the peripheral device 90 shown in FIG. 1 is connected.

The interface section 2 is connected to the common bus line 10 via the connection section 1. The connection section 1 has the same connection form as the connection section to the connector of the common bus line 10 of the package in which the logic circuit of the data processing apparatus shown in FIG. 1 is mounted. Therefore, use the vacant common bus line 10 connector, or
Alternatively, you can replace the data processing device package that is unnecessary for bus monitoring and connect the connection part 1 to the common bus line 10.
can be easily connected to. .

All bus signals 500 on the common bus line 10 are transferred to the collection control section 3, trigger generation section 4, control section and operation section 6 via a buffer at the interface section 2. The collection control unit 3 outputs stored information 600 in which bus signals 500 of some or all lines of the common bus line 10 consisting of a plurality of lines are selected. The storage control unit 5 stores the storage information 600 until the main control unit 6 outputs the control signal 200 for changing the operation.
is stored, and when it is updated to the highest address in the storage control unit 5, it returns to the lowest address and rewrites from the first address. In the main control section and the operation section 6, settings for a trigger pattern which is a pattern of the bus signal 500 to which the trigger signal 300 is to be output, a format editing mode for transferring information to the peripheral device 90, etc. are set in advance. Further, the main control section and the operation section 6 output an external signal 400 by manual operation or the like. The trigger generation section 4 sends the trigger signal 300 to the main control and operation section 6 when the trigger pattern set by the instruction from the main control and operation section 6 matches the bus signal 500, or when the external signal 400 is received. Forward.

When the main control unit and the operation unit 6 receive the trigger signal 300, a control signal 200 is sent to each control unit to change the operation.
give. At this time, the storage control section 5 stops the write operation and transfers the read information 700 to the editing control section 7. The editing control section 7 organizes the stored information 700 based on instructions from the main control section and the operation section 6, generates editing information 800 in accordance with the output format, and transfers it to the output control section 8. This output control section 8
outputs information to the peripheral device 90 at a transfer rate and data format suitable for the peripheral device 90. When the contents of all addresses in the storage control unit 5 are transferred and this series of operations is completed, the storage control unit 5 transfers the storage information 60.
The writing of 0 is resumed, and the control signal 2 is changed in the same manner as above.
00 outputs the memory contents to the peripheral device 90.
Furthermore, the same readout information 700 can be repeatedly transferred to and output from the peripheral device 90 by operating the main control section and the operation section 6.

Further, a buffer output line 1000 is outputted from the main control section and the operation section 6 so that the bus signal via the buffer can be observed externally. Common bus line 1 output to this buffer output line 1000
The selection of 0 is performed by the main control section and operation section 6, and the bus signal 500 of this common bus line 10 can be observed with a measuring instrument such as a synchroscope.

Further, the transfer destination of the read information 700 of the storage control unit 5 is switched from the editing control unit 7 to the storage data line 10.
0, the data can be transferred to the common bus line 10 via the interface section 2 and connection section 1. Switching of the transfer destination of the read information of the storage control unit 5 is controlled by the main control unit and the operation unit 6. When the transfer destination is set to the common bus line 10 through the storage data line 100, the main control unit and the operation unit 6 trigger signal 30
0 and outputs the control output 200 for changing the operation, the storage control unit 5 stops the write operation of the storage information 600, and then the storage control unit 5 outputs the control output 200 for changing the operation.
Common bus line 1
Transfer to 0. In this case, it is also possible to output the read information to the peripheral devices 40 and 60 of the data processing device shown in FIG. In other words, the memory data line 100
is a data line when the bus monitoring device responds as a storage address of a part of the main storage device 70 in FIG. Contains.

As described above, the present invention has the effect of facilitating the connection of the bus line by having a connection section having the same connection form as the connection section for connecting the package of the data processing device to the bus line.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a data processing device connected to an embodiment of the present invention, and FIG. 2 is a block diagram showing details of the bus monitoring device shown in FIG. 1. 10... Common bus line, 20... Central processing unit, 30, 50... Peripheral control unit, 40, 60, 9
0...Peripheral device, 70...Main storage device, 80...
Bus monitoring device, 1...Connection unit, 2...Interface unit, 3...Collection control unit, 4...Trigger generation unit, 5...Storage control unit, 6...Main control unit and operation unit, 7... ...Editing control section, 8...Output control section, 10
0...Storage data line, 200...Control signal,
300...Trigger signal, 400...External signal,
500...bus signal, 600...memory information, 70
0...Reading information, 800...Editing information, 10
00...Buffer output line.

Claims (1)

[Claims] 1. Trigger generation that generates a trigger signal when an address signal or data signal on a bus line of a data processing device matches preset address information or data information or when an external signal is received. storage means for writing and storing address signals or data signals on the bus line and stopping writing when receiving the trigger signal; and reading means for reading out the contents of the storage means in response to the trigger signal. and output means for outputting the storage content read by the reading means to a connected peripheral device without going through the bus line, and a connection form that is the same as that of the connection section of the data processing device connected to the bus line. A bus monitoring device comprising: 2. The bus monitoring device according to claim 1, wherein the output means includes editing means for sending edited information obtained by editing the read information read from the storage means to the peripheral device. 3. The reading means includes means for starting reading of the storage contents of the storage means in response to a command from the data processing device, and an interface section for supplying the read information read from the storage means to the bus line via the connection section. A bus monitoring device according to claim 1, characterized in that it includes: