JPS6339935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital logic device such as an electronic computer, and more particularly to the configuration of a digital logic device having a shift path.

Conventionally, in a digital logic device having this type of shift path, even if a register specifying an operation within the device holds specified information by the shift path, the register may hold new information in response to an activation signal during normal operation. In some cases, it was not possible to retain arbitrary information due to the shift pass, which caused trouble in diagnosing the device.

The present invention has been made in view of the above-mentioned conventional circumstances.Accordingly, an object of the present invention is to provide a means for controlling the register clock in a logic device having a shift path in the register, so that the register clock can be controlled during normal operation. provides a novel logic device that can facilitate device diagnosis by selectively holding information set in advance in a register by a shift operation, thereby allowing various operations to be set by the shift operation. There is a particular thing.

Another object of the present invention is to start normal operation after specifying an equivalent operation by shift operation when a predetermined operation cannot be specified by normal operation in the logic device (i.e., when a failure occurs). The purpose is to carry out a predetermined operation, confirm the operation, and diagnose the device.

According to the present invention, a plurality of register groups, a means for generating a clock inputted to a corresponding register group by an activation signal, a shift path of the register group, and a means for performing a shift operation using the shift path by a shift clock are provided. a logic device having a logic device including means for selectively blocking the clock, wherein data is preset in the register by a shift operation using the shift path when a failure occurs in the register group of the device or its input; Logic device including a shift path, characterized in that the output of the register is confirmed and diagnosed by applying a start signal and operating the register while the clock of the register is blocked by the clock blocking means. , is given.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

In a diagram showing an embodiment of the present invention, an example in which the present invention is used in a storage device will be described.
An R/W control register that receives the control signal 21, shift-in data 34, first startup clock 61, and shift designation signal 65 as input, and outputs the multi-bit R/W control register output 22 and first shift data 41. 1, normal/shift switching signal 33,
It receives a multi-bit startup clock control signal 29, startup signal 31, and R/W control register output 22 as input, and outputs a first clock blocking signal 56, a second clock blocking signal 53, a third clock blocking signal 54,
A control unit 5 outputting a fourth clock blocking signal 55, a read register clock 51, and an R/W timing 52, a plurality of bits of write data 23,
Second start clock 62, first shift data 4
1 and shift designation signal 65, and outputs a multi-bit write register output 24 and second shift data 42, a multi-bit address 25, a third activation clock 63,
Second shift data 42 and shift designation signal 65
an address register 3 which takes as input and outputs a multi-bit address register output 26 and third shift data 43, and a multi-bit read data 2.
7, fourth clock 64, third shift data 4
3 and a shift designation signal 65 as inputs, and a read register 4 which outputs a multi-bit read register output 28 and shift out data 35, a write register output 24, and an address register output 26.
and R/W timing 52 as input and read data 27 as output, and activation signal 3.
1. A first switching circuit 11 which receives the shift clock 32 and the first clock blocking signal 56 and outputs the first clock 61;
A second switching circuit 12 which receives the shift clock 32 and the second clock blocking signal 53 and has the second clock 62 as its output, and the activation signal 31, the shift clock 32 and the third clock blocking signal 54.
The third switching circuit 13 receives the clock 51, the shift clock 32, and the fourth clock blocking signal 55, and outputs the fourth clock 64. and a fourth switching circuit 14.

Here, the R/W control register 1 holds a multi-bit control signal 21 specifying reading or writing in synchronization with the first startup clock 61, and outputs the one bit as the first shift data 41. At the same time, the remaining bits are output as register output 22. Furthermore, when the register 1 is given the shift designation signal 65, it holds shift-in data in synchronization with the start-up clock 61 and outputs it as the first shift data 41 and the register output 22. Further, when the switching signal 33 specifies the normal operation, the startup clock control signal 29 is applied, and the register output 22 specifying the read operation is applied, the control unit 5 controls the timing 52 to specify the read operation.
Then, the read register clock 51 and the blocking signal specified by the starting clock control signal 29 among the first to fourth clock blocking signals 53 to 56 are output. In addition, a switching signal 3 specifying normal operation is also provided.
3. When the start clock control signal 29 and the register output 22 specifying a write operation are given, the control unit 5 selects the timing 52 for specifying write and the start clock among the first to fourth clock blocking signals 53 to 56. The blocking signal specified by the control signal 29 is output, but the clock 51 is not output.
When the switching signal 33 specifying the shift operation is applied, the control section 5 ignores the starting clock control signal 29 and does not output the signals 53 to 56 and the clock 51. If the blocking signals 56, 53 and 54 are not applied, the switching circuits 11-13 change the activation signal 31 to the first to third activation clock signals 61, respectively.
~63, while blocking signals 56, 53
and 54, circuits 11-13 block passage of activation signal 31. Further, when the shift clock 32 is applied, the circuits 11 to 13 unconditionally output the clock 32 as the first to third starting clock signals 61 to 63, respectively. When the blocking signal 55 is not applied, the switching circuit 14 outputs the read data clock 51 as the fourth activation clock signal 64, whereas when the blocking signal 55 is applied, the switching circuit 14 blocks the passage of the clock 51. . Also, when applied to the shift clock 32,
Circuit 14 unconditionally outputs clock 32 as fourth start-up clock signal 64.

Next, the operation of an embodiment of the present invention will be described with reference to the drawings.

First, the first operation will be explained. In the first operation, the switching signal 3 specifies normal operation.
3 is given to the control unit 5, and the blocking signal 5
The clock control signal 29 is not provided to the control section 5 so that none of the signals 4 to 56 are outputted from the control section 5. At this time, when the activation signal 31 is given, the circuits 11 to 13 use this signal 31 as activation clock signals 61 to 63, respectively, to clock the registers 1 to 3.
supply to. As a result, the R/W control signal 21, write data 23, and address 25 are stored in registers 1 to 3, respectively, and the contents of these registers 1 to 3 are respectively stored in R/W register output 22 and write register output 24. and is output as the address register output 26. signal 21
specifies a write operation, the control unit 5 supplies the write timing 52 to the storage unit 6 in response to the register output 22, so that the storage unit 6 performs the storage specified by the register output 26. Store the register output 24 at the address. On the other hand, signal 21
specifies a read operation, the control unit 5 supplies the read timing 52 to the storage unit 6 in response to the register output 22, so that the storage unit 6 performs the storage specified by the register output 26. The contents of the address are output as read data 27. Next, the control section 5 outputs a clock 51, which is passed through the circuit 14 to a starting clock 64.
This causes register 4 to store data 27.

Next, in the shift operation, that is, the second operation, the control section 5 is not supplied with the startup clock control signal 29, but is supplied with a switching signal 33 specifying the shift operation. A shift designation signal 65 is applied to registers 1-4. In such a state, when the shift clock 32 is supplied via the first to fourth clock switching circuits 11 to 14, the registers 1 to 4 receive shift-in data 34 and first to fourth clock switching circuits 11 to 14, respectively.
Third shift data 41, 42 and 43 are stored, and shift out data 35 is output from register 4. Every time this shift clock 32 is applied, shift-in data 34 → R/W control register 1 → first shift path 41 → write register 2 → second shift path 42 → address register 3 → third shift path 43 → read register 28
→The first bit is shifted in the order of shift-out data 35, so the shift operation causes R/
Any data can be input to the W control register 1, write register 2, address register 3, and read register 4, or data can be output from these registers.

Furthermore, in the third operation, a switching signal 33 specifying normal operation is given to the control unit 5, and
A clock control signal 29 is applied to the control section 5 such that at least one of the blocking signals 54-56 is outputted from the control section.

That is, at least one blocking signal designated by the clock control signal 29 is output from the control unit 5, and at least one switching circuit to which this at least one blocking signal is applied outputs the starting signal 31 or clock 51 as a starting clock. It will be like you don't do it. Therefore, even if the activation signal 31 is applied, the contents of the designated register (to which the activation clock is not applied) among the R/W control register 1, write register 2, address register 3, and read register 4 are not changed. It will remain as. In other words, if data is set in a predetermined register using a shift pass in advance by the second operation described above, the start clock is not input to the predetermined register by the third operation, so that the output of the register is not affected by the shift operation. It will operate based on the data input by.

That is, if at least one of the R/W control register 1, write register 2, address register 3, and read register 4 or its input becomes defective in the first operation, the second operation If data is input using the shift path, and the clock of the defective register is stopped and operated in the third operation, the defective location can be identified by confirming that it operates normally, and the defective register can be diagnosed. can be done.

As explained above, in a logic device including shift paths in a plurality of register groups, the present invention can configure a logic device that facilitates diagnosis by providing means for selectively blocking the startup clock of each register group. effective.

Although the present invention has been described above with respect to one preferred embodiment thereof, this is merely an illustrative example, and it goes without saying that the present invention is not limited only to the embodiment described herein.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 1...R/W (read/write) control register,
2...Write register, 3...Address register, 4
...read register, 5...control section, 6...storage section, 1
1, 12, 13, 14...first, second, third, fourth
switching circuit, 21...R/W (read/write)
Control signal, 22...R/W (read/write) control register output, 23...Write data, 24...Write register output, 25...Address, 26...Address register output, 27...Read data, 28...Read register output, 29 ...Start clock control signal, 31...Start signal, 32...Shift clock, 3
3... Normal/shift switching signal, 34... Shift-in data, 35... Shift-out data, 41, 4
2, 43...first, second, third shift data, 5
1...Read register clock, 52...R/W
(read/write) timing, 53, 54, 5
5, 56...first, second, third, fourth clock blocking signals, 61, 62, 63, 64...first, second,
3rd and 4th starting clocks, 65...shift designation signal.

Claims (1)

[Scope of Claims] 1. Storage means having a plurality of storage locations for storing or reading data in response to an operation designation signal; and one of the plurality of storage locations of the storage means.
address storage means for storing address data specifying one of the above, write data storage means for storing data to be written in the storage means, and read data storage means for storing data to be read from the storage means. Each of the storage means includes a storage means group that stores or outputs the data in synchronization with the startup clock signal only when the startup clock signal is supplied, and a storage means group that stores or outputs the data in synchronization with the startup clock signal; In order to set the data of
a shift path means configured as a shift register; and a blocking means for blocking the supply of the starting clock signal to the storage means specified by the blocking signal in response to a blocking signal corresponding to the starting clock control signal applied from the outside. , during the first operation, a start signal is given, and by not giving the start clock control signal, the supply of the blocking signal to the blocking means is stopped, and at the same time, the operation designation signal is supplied to the storage means; During the operation, the starting clock control signal is not applied, thereby stopping the supply of the blocking signal to the blocking means, and in response to the shift designation signal and the shift clock signal, the control signal is transmitted to the storage means group via the shift path means. Diagnostic data is transferred bit by bit from the outside, and in the third operation, the blocking signal is supplied to the blocking means in response to the activation clock control signal specifying a desired storage means in the group of storing means, and the 1. A logic device including a shift path, comprising a control means for supplying the operation designation signal to a storage means and causing the storage means to perform storage or readout corresponding to the operation designation signal.