JP4034757B2 - Method and apparatus for implementing a DRAM redundant fuse latch using SRAM - Google Patents

Description

  The present invention relates generally to the storage of fuse information, and more particularly to the storage of serial fuse information for a non-scannable static random access memory (SRAM) array in an embedded DRAM structure. And to structures and methods for searching.

  Dynamic random access memory (DRAM) arrays used in embedded applications rely on information stored in fuses (usually redundant information). This information must be loaded into the fuse latch in the embedded DRAM macro at startup before normal operation can begin. This information is conventionally loaded serially using a scan path connected between the fuse latches. In some applications, a centralized arrangement for fuse information (redundant information) is useful or it is desirable to reduce the area dedicated to fuse information.

  However, scan latches used to hold such information consume a large amount of space within the DRAM structure. The present invention described below avoids the need to use scan latches to maintain fuse information and achieves significant space savings when compared to conventional structures. Furthermore, the invention described below operates faster than devices based on conventional delocalized scan latches.

  The present invention provides a structure and method for serial storage and retrieval of fuse information for a non-scannable static random access memory (SRAM) array in an embedded DRAM structure. The SRAM array is part of the scan chain and is connected to the upstream and downstream latches that make up the scan chain. Various data are read serially into the scan chain. As data flows through the entire scan chain, the present invention uses a counter to count the number of bits read into the embedded DRAM structure. The counter can be included in the embedded DRAM structure. After the counter counts an amount equal to the number of bits stored in all downstream scan latches in the scan chain, the present invention loads the fuse information into the shift register. When the shift register is full, the present invention loads the contents of the shift register onto the SRAM line. The length of the shift register and SRAM line is equal to one fuse word. The present invention repeats the process of loading the shift register and loading the SRAM array until the SRAM array is full. The fuse information is read from the SRAM array simply by specifying an address in the SRAM array.

  The fuse information includes a list of activated fuses (fuses that have failed to replace a defective device with a properly operating device in the DRAM array). A shift register is used to collect serially received data and then load a number of bits in parallel into the SRAM (because the data is preferably written to the SRAM array in parallel rather than serially). . The process of loading the contents of the shift register into the SRAM line involves counting the bits loaded into the shift register, possibly in a second counter. Once the value of the second counter is equal to the size of the SRAM line, all the bits from the shift register are loaded simultaneously into the SRAM line in parallel.

  Another embodiment of the invention useful when the downstream length of the scan chain is unknown utilizes a FIFO operation. In this embodiment, data is continuously stored in the SRAM array using first-in, first-out (FIFO) operations until no data is read into the scan chain. More specifically, the FIFO operation writes the first bit to the first address of the SRAM array, and increments the address counter as each bit is written to the SRAM array. The FIFO operation continues to write additional bits to additional addresses in the SRAM array until the address counter reaches the maximum size of the SRAM array. Once the SRAM array is full, the present invention reads the first bit written to the array and outputs it to the downstream latch. The present invention then overwrites the first bit with the newest received bit. These output and overwriting processes are repeated for each subsequent bit in the SRAM array as additional bits are received.

  Therefore, in this embodiment, when data is received along the scan chain, the serially received data is written to each address in the SRAM array. After the SRAM array is full, the process overrides the oldest bit (first write bit) with the newest received bit of data. This override process ensures that once the data input to the scan chain is stopped, only the last part of the data input to the scan chain is maintained in the SRAM array.

  In the embodiment described above, a situation may arise where one fuse word is split between two lines of the SRAM array. Thus, the next two mechanisms of the present invention provide a search and realignment process corresponding to the splitting of one fuse line between two lines of the SRAM array. In each situation, the length of the SRAM line in the SRAM array is equal to one fuse word.

  The search process first calculates the offset by reading the last value from the address count register (this register counts the maximum number of bits in the SRAM, then resets and maintains a counter that starts counting again from zero To do). Data immediately after the value of the offset counter represents the oldest received bit, whereas data immediately before the offset counter represents the newest received data. The oldest data bit represents the first bit of fuse information. Thus, when a request is made for the address of a bit of fuse information, an offset must be added to the address to locate the physical address of that bit.

  This embodiment reads two SRAM lines with a single read. More specifically, the present invention reads the SRAM line that contains the physical address and the line immediately following it. Thus, the present invention reads the “first” SRAM line followed by the “second” SRAM line within a single system clock read cycle. This is because the present invention is expected to span the fuse word between two lines. The present invention calculates whether and how a fuse word spans between two lines by dividing the physical address by the SRAM line length. The division process yields an integer and a remainder. The remainder indicates the bit in the first SRAM line where the physical address is located (between the most significant bit and the least significant bit).

  The present invention combines the end of the first SRAM line with the beginning of the second SRAM line to output a single fuse word. The end of the first SRAM line includes the bits of the first SRAM line from the physical address to the least significant bit of the first SRAM line. The head of the second SRAM line is the bit of the second SRAM line from the most significant bit of the second SRAM line to the effective bit position that is one less than the effective bit position of the physical address in the first SRAM line. (It is obtained by subtracting 1 from the above-mentioned remainder value).

  Alternatively, immediately after reading all fuse information into the SRAM array, the present invention takes several clock cycles to realign the SRAM array so that all fuse words appear within a single SRAM line, thereby causing the SRAM line and “ Be aligned. This aspect of the invention is similar to the previous process and begins by calculating the offset as described above. This aspect of the invention then reads two SRAM lines (eg, reads a “first” SRAM line and an adjacent “second” SRAM line). The present invention stores the bit from the end of the first SRAM line in the first data register. This process then combines the end of the first SRAM line with the beginning of the second SRAM line to generate a single fuse word and to the address from which the first SRAM line was read during the read process. This single fuse word is stored (overwritten). This process is repeated for each subsequent line in the SRAM array, thereby ensuring that each line of the SRAM array contains a single fuse word.

  The present invention also includes embodiments that utilize multiple SRAM arrays within each embedded DRAM structure. In such an embodiment, the SRAM array is connected to upstream and downstream latches that make up the scan chain. In a process somewhat similar to that described above, this aspect of the invention reads scan data serially into the scan chain and stores the data in the SRAM array using a first-in first-out (FIFO) operation. This FIFO operation differs somewhat from the previously described FIFO operation in that the process first writes to the first SRAM array line, and once the first SRAM array line is full, the second Write the received additional bits to the same line of the SRAM array. In the FIFO operation, writing is performed on the subsequent lines of the first SRAM array only after the previous lines of the second SRAM array are full.

  In this situation, one fuse word may be divided between adjacent lines of separate SRAM arrays. Thus, the process of retrieving fuse information addresses this potential situation. Again, the length of the SRAM line in the SRAM array is equal to one fuse word, and the process maintains an offset counter that counts twice the fuse word size and then resets, so that the fuse word and SRAM line Start by calculating the offset between. Again, the value remaining in the offset counter at the end of writing to the SRAM represents the offset.

  The present invention reads one SRAM line from each of the SRAM arrays in a single read and recycle. Thus, the present invention reads the “first” SRAM line from one of the arrays and the subsequent “second” SRAM line from the other array within a single read cycle. This can include reading a line from the first SRAM array and then reading the same line from the second SRAM array. Alternatively, the read process can read one line from the second SRAM array, and then read subsequent lines in the first SRAM array. The present invention then combines the end of the first SRAM line with the beginning of the second SRAM line and outputs a single fuse word as described above.

  The present invention provides a number of advantages when compared to conventional embedded DRAM structures. The present invention can convert non-scannable memory elements that could previously only be loaded in parallel into scannable memory elements that can be loaded serially. This conversion allows the use of memory elements that were previously non-scannable in environments that require a serial method for loading / unloading memory elements. Non-scannable memory elements are typically more dense and have speed advantages over scannable memory elements. The present invention enables these advantages in an embedded DRAM structure. In particular, fuse information storage registers have been limited to implementations using large and slow scannable elements in the past because serial loading was required.

  The invention will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings.

  As previously mentioned, fuse information is conventionally loaded serially using a scan path connected between fuse latches. In some applications, centralized placement for fuse information latches is useful (redundant information) or it is desirable to reduce the area dedicated to fuse information. Instead of using scan latches, the present invention stores fuse information in SRAM.

  One embodiment discussed herein is useful when used with a stand-alone DRAM. In this embodiment, the shift register accumulates fuse information until it is full and then loads it into the SRAM. The loading of fuse information is started and stopped by information dedicated to the DRAM. However, the situation is different for a DRAM embedded in a scan chain. In such a situation, fuse information flows serially through the scan chain before or after information for upstream and downstream devices / latches in the scan chain. Thus, in DRAMs used in embedded applications, a problem arises because loading fuse information typically spans many DRAM macros and various other macros that use fuse information. In order to successfully load the correct fuse information for a particular DRAM macro into the SRAM, several issues must be addressed.

  First, the SRAM and its interface are similar to a collection of individual latches connected to the fuse scan chain and must remain compatible with all subsequent fuse latches. This allows all scan information to enter (and pass through) a virtual scan chain that is equal in length to the number of bits in the SRAM. If this fails, appropriate information is not loaded into all latches following the SRAM in the fuse scan chain.

  Second, the information stored in the SRAM must be accessible within a single clock cycle, where the clock cycle is the fuse information, in order to be somewhat similar to reading fuse information from individual latches. Defined by the relevant logic to access and interpret Information access must be independent of the actual physical location of fuse information in the SRAM.

  The method outlined below addresses these issues and provides a means of using SRAM for storing fuse information in a small space in a centralized arrangement. The final circuit of the SRAM and interface logic can be loaded and addressed like a registry array while saving significant area. The different embodiments of the invention described below all meet the above two requirements. More specifically, during fuse loading, the SRAM functions as a virtual scan chain of separate latches, and access fuse information from the SRAM within one system clock cycle without knowing the actual physical location in the SRAM. can do.

  The first embodiment shown in FIG. 1 represents the simplest scheme for implementation and requires the circuit to provide information regarding the number of bits in the fuse latch chain 105 following the target SRAM array 110. The programmable SRAM load start counter 122 counts up to this number of bits. After this point, all subsequent (downstream) bits pass and are loaded into the shift register 123 having a width equal to the word width of the SRAM 110. When the shift register 123 is full, it is loaded into the current address, thus guaranteeing one information fuse word per SRAM 110 word width. The start counter 122 is programmed to the total number of subsequent (downstream) bits. Using the address counter 121 and the bit counter 120, the shift giresta 123 is written in the SRAM 110 when carrying the value as shown in FIG. Then, access to fuse information from the SRAM 110 is performed simply by supplying a correct address and waiting for the read information to be output.

  Another embodiment of the present invention useful when the downstream length of the scan chain is unknown utilizes a first in first out (FIFO) operation, which is illustrated in FIG. In this embodiment, data is continuously stored in the SRAM array using a FIFO operation until no data is read into the scan chain. In this embodiment, no knowledge of the subsequent fuse latch scan chain is required. The interface logic for SRAM 110 creates a virtual register array for loading and information access.

  The address counter 121 increments continuously through the row space of the SRAM 110, while the bit counter 200 increments continuously through the word width of the SRAM 110. In each fuse scan clock cycle, the current data at the current address is read from the SRAM 110 in the first half of the clock cycle, then written during the second half of the fuse scan clock cycle, and the latest scan information bit is inserted at the position indicated by the bit counter. To do. The previous bit at this position is sent as scan output 201 of the SRAM 110 fuse block.

  Thus, the FIFO operation writes the first bit to the first address of the SRAM array 110 and increments the address counter 121 when each bit is detected by the bit counter 120. The FIFO operation continues to write additional bits to additional addresses in the SRAM array 110 until the address counter 121 reaches the maximum number of bits in the SRAM array 110. Once the SRAM array 110 is full, the present invention reads the first bit (oldest bit) written to the array and outputs it to the downstream latch 105 using the scan output 201. This is called read bit selection logic. The present invention then overwrites the first bit with the newest received bit. This is called scan and bit insertion logic. These output and overwriting processes are repeated for each subsequent bit in the SRAM array as additional bits are received. Each time this process reaches the end of the SRAM array, it goes back to the beginning and starts again.

  Thus, in this embodiment, when data is received along the scan chain, the received data is written serially to individual addresses within the SRAM array. After the SRAM array is full, the process overrides the oldest bit (first write bit) with the newest received bit of data (newest bit). This override process ensures that once the data input to the scan chain is stopped, only the last part of the data input to the scan chain (the latest data received) is maintained in the SRAM array. The last part of this data is appropriate data for a given SRAM. This is because the upstream latch maintains (and does not transfer) serial data for such upstream latch. For this reason, the last part of the data received by the target SRAM is fuse information related to a specific embedded DRAM.

  According to this embodiment, subsequent (downstream) scan bits can pass through this block 110 as if the SRAM block 110 consisted of individual serialized scan latches. Also, at the end of scan initialization, it is guaranteed that all necessary bits of fuse information are in SRAM 110.

  FIG. 3 shows a timing diagram of various signals when data is written into the SRAM 110 shown in FIG. The SRAM clock operates at twice the speed of the fuse clock and read / write clock. This is because the SRAM clock must be read and written during the time that a single read is taken by the scan and bit insertion logic input 200. As described above, the SRAM 110 can read old bits from the target address, output them through the read bit select logic output 201 within a single fuse clock read / write cycle, and write new bits to the same address. And shall be. The fuse clock and read / write clock are synchronized and the array select signal is always on. This indicates that the scan data flow through the SRAM continues throughout the entire scan operation.

  Access to the SRAM 110 is more complex. This is because the fuse word normally included in a single line of the SRAM 110 may be divided between two adjacent SRAM lines depending on the number of subsequent bits in the fuse scan chain. In other words, it is unlikely that the number of downstream bits is an even multiple of the number of bits in the SRAM 110, so the last bit of fuse information is unlikely to be the last logically addressed bit in the SRAM 110.

  The first approach in reading inconsistent SRAM 110 requires that SRAM 110 operate at twice the clock speed of the system clock of the logic it accesses (shown in the timing diagram of FIG. 5). This allows the memory to be accessed twice in each system clock read cycle. This is necessary to read two adjacent lines from the SRAM if the fuse word was split between two SRAM lines. The last value stored in the address count register 121 by the physical address offset device 400 (previously used for loading into the SRAM 110) is used here as an offset value, which is added to the normal logical input address to start the fuse word Gives the true physical position of.

  The fuse information is read from this physical address and stored in the first data register 402 (data register A). The next SRAM line following the line just read is then read and combined in the data mapping logic combiner 403 with the information from the first data register 402. The last value stored in address count register 121 (previously used to load into SRAM array 110) is used as a bit offset to store two partial lines of SRAM data (stored in register A along with the current SRAM output). A true fuse word from the data).

  Thus, in the embodiment shown in FIG. 4, the search process begins with the address counter register 121 (which maintains a counter that counts to the maximum number of bits in the SRAM, then resets and starts counting again from zero). Calculate the offset by reading the last value from. Therefore, the address count register 121 maintains the position of the SRAM where the latest data bits are written when the scan data circulates in the SRAM. A value remaining in the address count register 121 at the end of writing to the SRAM represents an offset.

  As described above, the number of storage positions (bits) in the SRAM may be different from the number of bits in the fuse data information. Thus, the fuse information word may not perfectly match the lines in the SRAM. For this reason, there is a possibility that the offset counter stops in the middle of the middle row (line) of the SRAM. The data immediately after the offset counter value represents the oldest received bit, while the data immediately before the offset counter represents the newest received data. The oldest data bit represents the first bit of fuse information. Therefore, when a request is made for the address of the first bit of fuse information, an offset must be added to the address to locate the physical address.

  If the result of exceeding the size of the SRAM occurs when the logical address and the offset are summed, this indicates that the physical address of the fuse information is actually arranged at the head of the SRAM array. As described above, when writing to the SRAM array, as described above, every time the end of the SRAM array is reached, the old bit is output to the downstream scan latch, and the address counter 121 returns to the top of the SRAM array and becomes old. This is because the bit is overwritten. Thus, in such a situation, the present invention determines the amount by which the calculated physical address is greater than the size of the SRAM array. This excess amount represents the correct physical address from the beginning of the SRAM array.

  This embodiment reads two SRAM lines in a single read. More specifically, the present invention reads the SRAM line containing the physical address and the line immediately following (following). Thus, the present invention reads the “first” SRAM line followed by the “second” SRAM line within a single system clock read cycle. This is because the present invention predicts that a fuse word will span between two lines. The present invention calculates whether and how a fuse word spans between two lines by dividing the physical address by the SRAM line length. The division process yields an integer and a remainder. The integer represents the line where the physical address is located. The remainder indicates the bit in the first SRAM line (eg column) where the physical address is located (between the most significant bit and the least significant bit).

  The present invention combines the end of the first SRAM line with the beginning of the second SRAM line to output a single fuse word. The end of the first SRAM line includes the bits of the first SRAM line from the physical address to the least significant bit of the first SRAM line. The head of the second SRAM line is the bit of the second SRAM line from the most significant bit of the second SRAM line to the effective bit position that is one less than the effective bit position of the physical address in the first SRAM line. (It is obtained by subtracting 1 from the above-mentioned remainder value).

  FIG. 5 shows a signal timing diagram used to read fuse information from the SRAM in the method described in the previous embodiment. The signals shown in FIG. 5 are similar to those shown in FIG. 3, except that the read / write clock is activated and maintained throughout the reading of fuse redundancy information. The SRAM clock operates at twice the speed of the system clock. This is because the SRAM clock must be read twice for all system clock drive requests for redundant information. As mentioned above, the SRAM 110 sometimes has to reconstruct a single fuse word from two SRAM words.

  Alternatively, immediately after loading all fuse information into the SRAM array, the present invention takes several clock cycles to realign the SRAM array so that all fuse words appear in a single SRAM line, thereby causing the SRAM line and “ Be aligned. By realigning the SRAM array, this embodiment avoids the need to read and align two lines (as described in the previous embodiment) each time the fuse word is accessed. This also eliminates the need to operate the SRAM clock at twice the system clock speed for reading.

  In this embodiment, after loading the fuse information, multiple clock cycles are used (at a time) to adjust the fuse word so that they do not overlap SRAM word boundaries. This aspect of the invention is similar to the previous process and begins by calculating the offset as described above. The present invention then determines the physical address of the first fuse word using the process described above. The present invention again reads two SRAM lines (eg, reads a “first” SRAM line and an adjacent “second” SRAM line). The present invention stores the bit from the end of the first SRAM line in the first data register. The process then couples the end of the first SRAM line to the beginning of the second SRAM line to generate a single fuse word that is converted into the first fuse word during the read process. Store (overwrite) the SRAM line at the read address. Prior to overriding the first portion of the first SRAM line, the present invention determines that these first bits (if the fuse word completely fills the SRAM array, finally, in the last fuse word) (Including the beginning of the second SRAM line).

  This process is repeated for each subsequent line in the SRAM array, thereby ensuring that each line of the SRAM array contains a single fuse word. Fuse word reconstruction is accomplished using a structure including an eight-state finite state machine (FSM) 600 shown in FIG. To avoid unnecessary data alignment, this aspect of the invention includes a fixed address counter 601 that starts counting from zero and counts up to the number of fuse words, after which the alignment process stops. The number of cycles required to fix the fuse word position (counted by the fixed address counter 601) is substantially fixed at 3 * n, where n is the number of SRAM words. If the number of words in the SRAM is equal to the number of fuse words, the FSM 600 must perform a read operation (state 4), a match word construction operation (state 5), and a write operation (state 6) for each word in the SRAM. Don't be. As a result, three operations are required to align each fuse word.

  This realignment operation begins when the “fixed” signal becomes active. This signal can be supplied externally or can be automatically generated upon completion of fuse loading or the start of BIST system testing. When the FSM is finished, it provides a “fixed end” signal that remains active until the macro resets, and the FSM remains in its stopped state. The normal / test operation can then be started.

  As shown in the state diagram of FIG. 7, the FSM operates very similar to the process described above. An address is generated and the address offset contained in the original address count register is combined (state 1). Data from this address is read into the temporary storage register A (state 2). This data is then shifted to the second temporary register B (state 3), another read of the next SRAM word is made (state 4), and the result is returned to the first (made up) temporary register Store in A (state 5). Using the bit offset contained in the bit count register, an actual fuse word is generated from the data in registers A and B and written to the SRAM array 110 (also in state 5). The data in register A is then shifted to register B (state 6), and SRAM 110 is again read into register A (the arrow returns to state 4). The timing signal for this process is shown in FIG. The system clock matches the SRAM clock. Performing a read operation in state 4, array selection is active during both states 4 and 5, the next SRAM line can be read, and then the matched fuse word can be written to the SRAM. This process is repeated for all words in the SRAM 110 array until all fuse words are fixed and aligned with the SRAM word boundary (state 7).

  After aligning the fuse word with the SRAM word, the SRAM array can be accessed once for each normal read access input. The physical SRAM address is again calculated by combining the offset stored in the address count register with the normal logical input address. However, in this embodiment, the offset is adjusted so that the physical address starts with the most significant bit of the corresponding SRAM line. In the previous embodiment, the offset is divided by the number of bits in the SRAM line, and the remainder in the division process represents the bit position in the given SRAM line where the fuse word begins. However, in this embodiment, the fuse word is realigned by the SRAM word line, so if this remainder is subtracted from the offset and the offset is added to the logical fuse word address, the generated physical address will be the corresponding SRAM line. It starts with the most significant bit.

  The present invention also includes yet another embodiment that utilizes multiple SRAM arrays 900, 901 within each embedded DRAM structure, as shown in FIGS. In such an embodiment, the SRAM arrays 900, 901 are connected to the upstream and downstream latches 105 that make up the scan chain. In a process somewhat similar to that described above, this aspect of the invention reads data serially into the scan chain and stores the data in SRAM arrays 900, 901 using a first-in first-out (FIFO) operation. This FIFO operation is slightly different from the FIFO operation described above. In this process, the first SRAM array 900 line is first written, and once the first SRAM array line is full, the second SRAM array is filled. The received additional bits are written to the same line of the array 901. In other words, this embodiment treats the lines next to adjacent SRAM arrays 900, 901 as one double size SRAM word line. In the FIFO operation, writing to the subsequent lines of the first SRAM array 900 is performed only after the previous lines of the second SRAM array 902 are full.

  This embodiment allows access to the SRAM 110 immediately after loading the fuse information, and only some simple logic is required to generate the physical word address of the desired logical fuse word. This embodiment eliminates the need to run the SRAM 110 with multiple clocks (as described above) and further eliminates the need to realign the fuse word with the SRAM 110 word line.

  This makes it possible to use either two SRAMs or a single multi-port SRAM that allows two simultaneous reads / writes. The use of two separate SRAMs is illustrated in the drawings. However, it will be appreciated by those skilled in the art (after reading this disclosure) that the present invention is not so limited and the use of multi-port SRAMs is similar. In a multi-port SRAM, instead of reading / writing between SRAMs, this method reads / writes between the upper and lower halves of the same SRAM (virtually creating two SRAMs).

  Loading to the SRAM array is very similar to the method described above in connection with FIG. One difference in the embodiment shown in FIG. 9 is that the bit count now counts up to twice the fuse word / SRAM 110 word width and requires a 2X count 903. As a result, in each line of the SRAM array, the bit from the most significant bit of the SRAM 900 is effectively written to the least significant bit of the SRAM 901 (a line lined up horizontally is treated as a single double size line). Using this process, the fuse word will be contained in a single SRAM word or divided between words from SRAM 900 and SRAM 901. However, this embodiment eliminates the need to read lines continuously from a single SRAM memory at twice the system clock rate (as in previous embodiments). This is because two adjacent SRAM lines are always in separate SRAM arrays 900, 901 that can be read simultaneously (in parallel). Thus, this embodiment can read in parallel SRAM wordlines that may include the beginning and end of a partial fuse word in a single clock read cycle. The signal timing diagram of FIG. 10 shows signals when data is written to the SRAM 900 and the SRAM 901, and is the same as the timing diagram of FIG. 3 illustrating the loading of data to the single SRAM 110. While the array select signal is active, the SRAM clock operates at twice the frequency of the fuse and read / write clock. This is because the SRAM clock must be read and written during the time it takes a single read by the scan and bit insertion logic input 200. As described above, the SRAM (900 or 901) reads the old bit from the address of interest and outputs it via the read bit select logic output 201 in a single fuse clock read / write and at the same address the new Must be able to write bits.

  In this embodiment, the present invention writes the first bit to the first bit address of the first line of the first SRAM array and then writes the additional bit to the additional address in the first line of the first SRAM array. A first counter is incremented as each additional bit is written to the first line of the first SRAM array. When the first counter reaches the maximum size (eg, word line size) of the first line of the first SRAM array, the method repeats the increment and write process for the first line of the second SRAM array. Similarly, when the counter reaches the maximum size of the first line of the second SRAM array, the method repeats the increment, write, and repeat process for subsequent lines in both SRAM arrays.

  During the write process described above, the present invention simultaneously increments the second counter as each bit is written to the SRAM array. When the second counter reaches the maximum size of both SRAM arrays, the method outputs the first bit at the first bit address of the first line of the first SRAM array to the downstream latch, and the first of the first SRAM array. The first bit in the first bit address of the line is overwritten with the newest received bit. The present invention then repeats output and overwriting for each subsequent bit in the SRAM array (in the order in which the bits were written to the SRAM array) when receiving additional bits until all fuse data has been received. Similar to the process described above, this causes fuse information to be included in the most recent received bit in the serial bitstream in both SRAM arrays.

  Access to the fuse word is done simply by generating a physical address for the fuse word (using the final value stored in the address count register as an offset) based on the logical fuse word address. The next SRAM word is simultaneously read from the opposite SRAM 110. The actual fuse word is then constructed from the two SRAM 110 words based on the bit offset stored in the bit count register.

  More specifically, the access process maintains an offset counter 400 that counts to the number of bits in both SRAM arrays 900, 901 and then resets as the data is written to the SRAM to calculate the offset. The value remaining in the offset counter at the end of writing to the SRAM represents the offset. The present invention uses an address multiplexer 1100 and an address incrementer 1101 to determine the physical location of the first bit within the desired fuse word request, as shown in FIG.

  These devices 1100, 1101 add the logical address of the desired fuse word to the offset to generate the total physical location. Device 1100, 1101 then divides the total physical position by a divisor (which is equal to twice the number of bits in the SRAM word line), resulting in an integer and a remainder. The integer represents the physical address row, and the remainder represents the column address. If the remainder is greater than the number of bits in the SRAM word line, the column address is in the second SRAM array and is equal to the remainder minus the number of bits in the SRAM word line. Thus, in this situation, the multiplexer 1100 will select the second SRAM 901. If the remainder is less than or equal to the number of bits in the SRAM word line, the column address is in the first SRAM array and is equal to the remainder. Thus, in this situation, multiplexer 1100 will select the first SRAM 900.

  The present invention then simultaneously reads one SRAM line from each of the SRAM arrays in a single read and recycle to read the first SRAM line and the subsequent second SRAM line. If the column address (determined as described above) is in the first SRAM array 900, the present invention reads the first line from the first SRAM array 900 and then the same second from the second SRAM array 901. Read 1 line. In such a situation, the line read from the first SRAM array 900 includes the “first” SRAM line, and the line read from the second SRAM array 901 includes the “second” SRAM line. Alternatively, if the column address is in the second SRAM array 901, the present invention reads the first line from the second SRAM array 901 and then the first SRAM line immediately after the first line in the first SRAM array 900. Read the second line at 900. Unlike the previous example, in this situation, the first line from the second SRAM array 901 includes the “first” SRAM line, and the first line from the first SRAM array 901 is “ Includes a "second" SRAM line.

  Using data multiplexer 1102, the present invention combines the end of the “first” SRAM line with the beginning of the “second” SRAM line and outputs a single fuse word to data mapping logic 403. The end of the first SRAM line includes the bits of the first SRAM line from the physical location to the least significant bit of the first SRAM line, the beginning of the second SRAM line being the most significant of the second SRAM line It includes bits from the second SRAM line from the bit to a valid bit position that is one less than the valid bit position of the physical position in the first SRAM line.

  The signal timing diagram of FIG. 12 shows signals when executing the reading operation. The signal is similar to that shown in FIG. 10, but since the present invention reads continuously during operation, the read / write signal is maintained in the active position throughout the process. Other signals operate in the same manner as described above with reference to FIG.

  The present invention can convert non-scannable memory elements that could previously only be loaded in parallel into scannable memory elements that can be loaded serially. This conversion is extremely useful in implementing faster, higher density memories that can be loaded through the scan chain. Storing local fuse information for embedded memory structures is one application of the present invention. The present invention can improve the storage of fuse information in embedded SRAM, CAM, and other memory types as well as embedded DRAM memory. Another important application of the present invention is to convert small read-only memories that can be initialized by scanning from individual scannable elements to faster, higher density SRAMs. These scannable read only memories (SROMs) are typically used to store BIST microcode instructions, and all BIST performance can be greatly improved by converting the SRAM to a scannable SRAM. .

  While the invention has been described in terms of a preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the scope and spirit of the claims.

1 is a schematic diagram of one embodiment of an embedded DRAM structure of the present invention that includes fuse information in SRAM. FIG. 1 is a schematic diagram of one embodiment of an embedded DRAM structure of the present invention that includes fuse information in SRAM. FIG. FIG. 3 is a signal timing diagram illustrating signals used to store fuse information in the structure shown in FIG. 2. 1 is a schematic diagram of one embodiment of an embedded DRAM structure of the present invention that includes fuse information in SRAM. FIG. FIG. 5 is a signal timing diagram illustrating signals used to retrieve fuse information in the structure shown in FIG. 4. 1 is a schematic diagram of one embodiment of an embedded DRAM structure of the present invention that includes fuse information in SRAM. FIG. It is the schematic of the state in the state machine shown in FIG. FIG. 7 is a signal timing diagram illustrating signals used to match fuse information in the structure shown in FIG. 6. 1 is a schematic diagram of one embodiment of an embedded DRAM structure of the present invention that includes fuse information in two SRAM arrays. FIG. FIG. 10 is a signal timing diagram illustrating signals used to store fuse information in the structure shown in FIG. 9. 1 is a schematic diagram of one embodiment of an embedded DRAM structure of the present invention that includes fuse information in SRAM. FIG. FIG. 12 is a signal timing diagram illustrating signals used for retrieving fuse information in the structure shown in FIG. 11.

Claims (35)

In a method of serial storage and retrieval of fuse information for a static random access memory (SRAM) array in an embedded dynamic random access memory (DRAM) structure, the SRAM array is connected to upstream and downstream latches that make up a scan chain. And the method comprises
Reading data serially into the scan chain;
Counting the number of bits read into the embedded DRAM structure using a counter;
Loading the fuse information into a shift register after the counter has counted an amount equal to the number of bits stored in all downstream scan latches in the scan chain;
When the shift register is full, loading the contents of the shift register into the SRAM line of the SRAM array;
Repeating the process of loading the shift register and loading the SRAM array until the SRAM array is full;
Reading the fuse information from the SRAM array by designating an address in the SRAM array;
Having a method. The method of claim 1, wherein the number of bits in the shift register and the SRAM line is equal to the number of bits in the fuse word. The method of claim 1, wherein data is written to the SRAM array in parallel operation. The method of claim 1, wherein the downstream scan latch is downstream of the embedded DRAM structure. The process of loading the contents of the shift register into the SRAM line includes a step of counting bits loaded into the shift register in a second counter, and once the value of the second counter is the size of the SRAM line And loading all of the bits from the shift register simultaneously into the SRAM line in parallel. In a method of serially storing fuse information in a static random access memory (SRAM) array within an embedded dynamic random access memory (DRAM) structure, the SRAM array is connected to upstream and downstream latches that make up a scan chain. The method
Reading data serially into the scan chain;
Storing the data in the SRAM array using a first in first out (FIFO) operation until no data is read into the scan chain ;
And the FIFO operation is
Reading the SRAM line of the SRAM array;
Sending a bit of the SRAM line at a position indicated by a bit counter that increments across the word width of the SRAM array to the downstream latch;
Inserting the newest received bit at the position indicated by the bit counter and writing it back to the SRAM line;
Method. The FIFO operation comprises the steps of incrementing an address counter as each bit of data is read into the SRAM array and writing each bit of received data to subsequent bits in the SRAM array. Item 6. The method according to Item 6. The FIFO operation is
Writing a first bit to a first bit address of the SRAM array;
Writing additional bits to additional addresses of the SRAM array;
Writing a counter to each additional bit written to the SRAM array;
And when the counter reaches the maximum size of the SRAM array, the method comprises:
Outputting the first bit to the downstream latch;
Overwriting the first bit with the newest received bit;
Repeating the output and the overwriting for each subsequent bit in the SRAM array when receiving additional bits;
The method of claim 6 comprising: 9. The method of claim 8, wherein after the write process is complete, the SRAM array includes only the most recent received bits. In a method for retrieving fuse information from a static random access memory (SRAM) array in an embedded dynamic random access memory (DRAM) structure, the SRAM array is connected to upstream and downstream latches comprising a scan chain, and The length of the SRAM line in the SRAM array is equal to the fuse word, and the fuse word stored in the SRAM array may straddle two SRAM lines, the method comprising:
Calculating an offset;
Determining the physical location of the first bit in the desired fuse word request by adding the logical address of the first bit of the desired fuse word to the offset;
Reading two SRAM lines to read a first SRAM line including the physical location of the first bit and a second SRAM line immediately after the first SRAM line;
Combining the end of the first SRAM line with the beginning of the second SRAM line to output the desired fuse word;
Having a method. The step of calculating the offset comprises maintaining an offset counter that counts to the number of bits in the SRAM array and then resets when data is written to the SRAM array, and at the end of writing to the SRAM array The method of claim 10, wherein a value remaining in the offset counter represents the offset. The end of the first SRAM line has bits of the first SRAM line from the physical location to the least significant bit of the first SRAM line, and the head of the second SRAM line is 11. The bits of the second SRAM line from a most significant bit of the second SRAM line to a valid bit position that is one less than a valid bit position of the physical position in the first SRAM line. Method. The method of claim 10, wherein the step of reading the two SRAM lines is performed in a single system clock cycle. The method of claim 10, wherein the combining process outputs a single fuse word. In a method for realigning fuse information in a static random access memory (SRAM) array within an embedded dynamic random access memory (DRAM) structure, the SRAM array is connected to upstream and downstream latches that make up a scan chain; The length of the SRAM line in the SRAM array is equal to the fuse word, and the fuse word stored in the SRAM array may straddle two SRAM lines, the method comprising:
Calculating an offset;
Determining a physical location of a first bit of a first fuse word by adding a logical address of the first bit of the first fuse word to the offset;
Reading two SRAM lines to read a first SRAM line including the physical location and a second SRAM line immediately after the first SRAM line;
Storing bits from the end of the first SRAM line in a first data register;
Storing a bit from the tip of the second SRAM line in a second data register;
Combining the end of the first SRAM line with the head of the second SRAM line to output a single fuse word;
Storing the single fuse word in the first SRAM line and overwriting the first SRAM line with the fuse word;
Repeating the process from the desired process to the process of storing the single fuse word for all remaining fuse words;
Having a method. The step of calculating the offset comprises maintaining an offset counter that counts to the number of bits in the SRAM array and then resets when data is written to the SRAM array, and at the end of writing to the SRAM array The method of claim 15, wherein a value remaining in the offset counter represents the offset. The end of the first SRAM line has bits of the first SRAM line from the physical location to the least significant bit of the first SRAM line, and the head of the second SRAM line is 16. The bits of the second SRAM line from a most significant bit of the second SRAM line to a valid bit position that is one less than a valid bit position of the physical position in the first SRAM line. Method. The method of claim 15, wherein the first fuse word comprises a first logical fuse word of fuse words stored in the SRAM array. The method of claim 15, wherein after the repeating step is completed, all fuse words are aligned with SRAM array words. In a method of serially storing fuse information in a number of static random access memory (SRAM) arrays within an embedded dynamic random access memory (DRAM) structure, the SRAM array is connected to upstream and downstream latches that form a scan chain. And the method comprises
Reading data serially into the scan chain;
Storing the data in the SRAM array using a first in first out (FIFO) operation;
The FIFO operation first writes to the first line of the first SRAM array, and once the first line of the first SRAM array is full, the second SRAM array Write the received additional bits to the same first line, and the FIFO operation is the first SRAM following the first line only after the first line of the second SRAM array is full. A method of writing to subsequent lines of the array. The FIFO operation comprises the steps of incrementing an address counter as each bit of data is read into the SRAM array and writing each bit of received data to subsequent bits in the SRAM array. Item 20. The method according to Item 20. The FIFO operation is
Writing a first bit to a first bit address of the first line of the first SRAM array;
Writing additional bits to additional addresses in the first line of the first SRAM array;
Writing a first counter as each additional bit is written to the first line of the first SRAM array;
And when the first counter reaches a maximum size of the first line of the first SRAM array, the method includes the increment and the first line of the second SRAM array. Repeat the burning process
If the counter reaches the maximum size of the first line of the second SRAM array, the method repeats the increment, write, and repeat process for subsequent lines of both SRAM arrays. Item 20. The method according to Item 20. The method further comprises:
Writing each bit to the second SRAM array includes incrementing a second counter, and when the second counter reaches the maximum size of both the SRAM arrays, the method comprises:
Outputting the first bit at the first bit address of the first line of the first SRAM array to the downstream latch;
Overwriting the first bit in the first bit address of the first line of the first SRAM array with the newest received bit;
Receiving the additional bits, repeating the output and overwriting steps for each subsequent bit in the SRAM array in the order in which the bits were written to the SRAM array;
23. The method of claim 22, comprising: 24. The method of claim 23, wherein after the write process is complete, the SRAM array includes only the most recent received bits. In a method for retrieving fuse information from multiple static random access memory (SRAM) arrays in an embedded dynamic random access memory (DRAM) structure, the SRAM array is connected to upstream and downstream latches that make up a scan chain. The SRAM line length in the SRAM array is equal to the fuse word, and the fuse word stored in the SRAM may straddle two SRAM lines in different SRAM arrays, the method comprising:
Calculating an offset;
Using the offset to determine the physical position of the first bit in the desired fuse word request;
Reading one SRAM line from each of the SRAM arrays in a single read cycle and reading the first SRAM line and the next second SRAM line in the single read cycle;
Combining the end of the first SRAM line with the beginning of the second SRAM line to output a single fuse word, wherein the end of the first SRAM line is from the physical location to the The first SRAM line has bits up to the least significant bit of the first SRAM line, and the head of the second SRAM line starts from the most significant bit of the second SRAM line. Having the bits of the second SRAM line up to one less significant bit position than the effective bit position of the physical position in the SRAM line; and
Method. The step of calculating the offset comprises maintaining an offset counter that counts up to the number of bits in both SRAM arrays and then resets when data is written to the SRAM, and at the end of writing to the SRAM 26. The method of claim 25, wherein a value remaining in the offset counter represents the offset. The process of determining the physical position of the first bit in the desired fuse word request comprises:
Adding a logical address of the desired fuse word to the offset to generate a total physical location;
Dividing the total physical position by a divisor that is twice the number of bits of a line in one of the SRAM arrays to generate an integer and a remainder, wherein the integer represents a row of the physical address; The remainder represents a column address, and if the remainder is greater than the number of bits of one of the lines of the SRAM array, the column address is in the second SRAM array, and from the remainder, one of the SRAM arrays If the number of bits in the line is equal to and the remainder is less than or equal to the number of bits in one of the lines of the SRAM array, the column address is in the first SRAM array and the remainder and Equal steps, and
26. The method of claim 25, comprising: The reading process is:
If the column address is in the first SRAM array, read the first line from the first SRAM array, then read the same first line from the second SRAM array, and The first line from has the first SRAM line, and the first line from the second SRAM array has the second SRAM line; and
If the column address is in the second SRAM array, the first line is read from the second SRAM array and then the first line immediately after the first line in the first SRAM array. A second line of the SRAM array, wherein the first line from the second SRAM array has the first SRAM line, and the first line from the first SRAM array is the A step adapted to have a second SRAM line;
28. The method of claim 27, comprising one of: 26. The method of claim 25, wherein the SRAM array comprises a single multi-port SRAM. A dynamic random access memory (DRAM) device,
A serial bitstream input connected to multiple upstream bit latches;
A serial bitstream output connected to a plurality of downstream bit latches;
The serial bit stream input and the connection with a serial bit stream output, possess a SRAM array to maintain the fuse information for the DRAM device, performing a method according to any one of claims 1 to 29 DRAM device. A machine readable program storage device that unambiguously embodies a program of instructions executable by the machine to fuse information in a static random access memory (SRAM) array in an embedded dynamic random access memory (DRAM) structure. The SRAM array is connected to the upstream and downstream latches constituting the scan chain, and the SRAM line length in the SRAM array is equal to the fuse word, and the SRAM array is connected to the SRAM. The stored fuse word may span two SRAM lines, and the method includes:
Calculating an offset;
Determining a physical location of a first bit in a first fuse word by adding a logical address of the first bit of the first fuse word to the offset;
Reading two SRAM lines to read a first SRAM line including the physical location and a second SRAM line immediately after the first SRAM line;
Storing bits from the end of the first SRAM line in a first data register;
Storing a bit from the tip of the second SRAM line in a second data register;
Combining the end of the first SRAM line with the head of the second SRAM line to output a single fuse word;
Storing the single fuse word in the first SRAM line and overwriting the first SRAM line with the fuse word;
Repeating the process from the desired process to the process of storing the single fuse word for all remaining fuse words;
Having a method. The step of calculating the offset comprises maintaining an offset counter that counts to the number of bits in the SRAM array and then resets when data is written to the SRAM array, and at the end of writing to the SRAM array 32. The method of claim 31 , wherein a value remaining in the offset counter represents the offset. The end of the first SRAM line has bits of the first SRAM line from the physical location to the least significant bit of the first SRAM line, and the head of the second SRAM line is from the most significant bit of the second SRAM line, having a bit of the second SRAM line to one less effective bit positions than the effective bit positions of the physical position in the first SRAM line, according to claim 31 Method. 32. The method of claim 31 , wherein the first fuse word comprises a first logical fuse word of fuse words stored in the SRAM array. 32. The method of claim 31 , wherein after the repeating step is complete, all fuse words are aligned with SRAM array words.

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