JPS6312038A - Defect information collecting system - Google Patents

Abstract

PURPOSE:To collect the information of a memory element in a logical device at a high speed by providing an initial value setting instruction from a diagnosing control device to an address register, an address updating instruction and a contents reading bus of a reading register. CONSTITUTION:When the contents of a memory element 4 are to be read at the time of the defect, a diagnosing control device 3 supplies a changing-over signal to a changing-over part 22 and the initial address value supplied to a memory element 4 is set through an initial value setting instructing signal line 200 to a register 20. The register 20 supplies the address data to be latched through the changing-over part 22 to a memory element. For the address data latched to the register 20, an adder 5 is operated by an updating instruction signal supplied from the diagnosing control device 3 through an address updating instruction signal line 202, the data corresponding to the adding address are supplied to a register 21 with a constant value at a constant part 23, the register 21 latches this value and supplies it through a reading bus 201 to the diagnosing control device 3. Thus, the memory element information can be collected at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault information collection method for a faulty device, and more particularly to a fault information collection method for a faulty device including a storage element.

[Conventional technology]

Conventionally, as a failure information collection method for a logic device including a storage element, information on the storage element has been collected using a shift path. In other words, in order to read the information of the memory element, an address register or register that holds the address information of the memory element,
There is a read register that holds information of the storage element according to the address information, and since these registers are connected by a shift path, the address information is first shifted into the address register by the shift path. next,
By issuing one step of the clock of the logic device, the information of the storage element according to the address information is stored in the read register. Next, the information in the read register is shifted and aligned using a shift pass to collect information on the storage element according to the address information.

By performing this operation for all addresses of the memory element, information on the memory element is collected.

[Problem that the invention seeks to solve]

The above-mentioned conventional memory element information collection involves a shift-in to the address register, a clock shift to store the contents of the memory element according to the address information in the read register, and a shift-out of the read register contents. Since the operation is performed on all addresses of the memory element, there is a drawback that a large amount of time is required to collect information on the memory element.

[Means for solving problems]

The method of the present invention is a fault information collection method for a logic device having a memory element and a shift path configured by sequentially connecting a plurality of flip-flops in series. an address register that temporarily stores address data of the storage element supplied from the address register; and an address register that temporarily stores address data of the storage element supplied from the address register, and a fixed value set for the address data supplied from the address register in response to an update signal supplied externally in synchronization with the non-stop clock. an addition means for adding and supplying the address data to the address register; and an address supply means for receiving the address data from the address register and supplying the address data to the storage element in response to a switching signal supplied from the outside in the event of a failure. , a read register that operates with the non-stop clock, temporarily stores data read from the storage element, and supplies the data to the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The fault information collection method shown in FIG. 1 includes a logic device 1 and a diagnostic control device 3, and the logic device 1 includes at least a storage element 4,
It includes a register 11, a register 12, and a storage element information reading section 2.

In normal operation of the logic device 1, address data is supplied via the signal line 209 and set in the register 11. The output of the register 11 is connected to a switching unit 22 (as described later, the switching unit 22 normally selects the output of the register 11), and a signal line 2.
07 to the storage element 4, the corresponding data is read out to the register 12, and is supplied to other parts via the signal line 210. Registers 11 and 12 are on shift paths 204, 205.2 for collecting fault data in the event of a fault.
06 to the diagnostic control device 3.

The storage element information reading section 2 includes registers 20 and 21.
, a switching section 22, an adder 5, and a constant section 23.The switching section 22 is supplied with the output of the register 20 and the output of the register 11, and normally the output of the register 11 is selected. The output of the register 20 is selected in response to a switching signal supplied from the register 3 via the switching signal line 203 (this is supplied when the contents of the storage element are not read out in the event of a failure). Further, in the event of a failure, the supply of clock signals to each section of the logic device 1 is stopped, but the clock signal is continuously supplied to the memory element information reading section 2 without interruption.

Next, the operation of this embodiment will be explained.

When it is desired to read the contents of the memory element 4 in the event of a failure, the diagnostic control device 3 outputs the switching signal &! A switching signal is supplied to the switching unit 22 via the initial value setting instruction signal line 200
An initial address value to be supplied to the storage element 4 is set in the register 20 via the register 20 . As mentioned above, even in the event of a failure, the clock signal is continuously supplied to the memory element information reading section 2 without interruption, so the register 20 supplies address data to be latched one after another to the memory element via the switching section 22. do. Regarding the address data latched in the register 20, the adder 5 is operated by an update instruction signal supplied from the diagnostic control device 3 via the address update instruction signal line 202, and the constant value in the constant section 23 is added to the data corresponding to the address. The signal is supplied to the register 21 via the signal line 208.
latches this and supplies it to the diagnostic control device 3 via the read path 201.

In this manner, in this embodiment, corresponding data from the storage element 4 can be read out and collected at high speed in response to address data supplied from the diagnostic control device 3.

〔Effect of the invention〕

As explained above, the present invention provides an address register that operates with a non-stop clock in a logic device including a storage element, an adder that updates the contents of this address register, and a read register that stores the contents of the storage element. By providing an initial value setting instruction from the diagnostic control device to the address register, an address update instruction, and a read path for reading the contents of the read register, information in the storage elements in the logic device can be read at high speed. It has the effect of being collectable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Logic device, 2...Storage element information reading unit,
3...Diagnostic control device, 4...Storage element, 5...Adder, it, 12.20.21...Register, 22...
- Switching section, 23...Constant section, 200...Initial setting instruction signal line, 201...Reading path, 202...Address update instruction signal line, 203...Switching signal line, 20
4,205.206...Shift pass.

Claims (1)

[Scope of Claims] In a failure information collection method for a logic device having a memory element and forming a shift path by sequentially connecting a plurality of flip-flops in series, there is provided an adding means that operates with a non-stop clock and is initialized from the outside. an address register that temporarily stores address data of the storage element supplied from the address register; and an address register that temporarily stores address data of the storage element supplied from the address register, and a fixed value set for the address data supplied from the address register in response to an update signal supplied externally in synchronization with the non-stop clock. an addition means for adding and supplying the address data to the address register; and an address supply means for receiving the address data from the address register and supplying the address data to the storage element in response to a switching signal supplied from the outside in the event of a failure. and a read register which operates with the non-stop clock, temporarily stores data read from the storage element, and supplies the data to the outside.