JPS629625A - Method for formation of microscopic electrode - Google Patents
Method for formation of microscopic electrodeInfo
- Publication number
- JPS629625A JPS629625A JP14833085A JP14833085A JPS629625A JP S629625 A JPS629625 A JP S629625A JP 14833085 A JP14833085 A JP 14833085A JP 14833085 A JP14833085 A JP 14833085A JP S629625 A JPS629625 A JP S629625A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- impurity region
- silicon dioxide
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は微細電極の形成方法に係わり、特にPN接合の
形成後、各領域に接続される電極を所定寸法に精度よく
穿設できる微細電極の形成方法に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for forming a microelectrode, and particularly to a microelectrode that allows electrodes to be connected to each region to be precisely drilled to predetermined dimensions after forming a PN junction. The present invention relates to a method of forming.
〈従来の技術〉
第2図(a)乃至(f)は従来例を表わす工程図であり
、第2図(a)は熱酸化膜1の成長した半導体基板2を
表わしている。 熱酸化膜1はリソグラフィ一工程を経
て開口3が穿設され(第2図(b))、該開口3から不
純物が拡散されてベース領域4が形成される。 拡散工
程中にベース領域4上には酸化膜5が成長され、熱酸化
膜1と酸化膜5との間には段差が形成される(第2図(
C))。 続いて、酸化膜5にはエミッタ拡散用の開口
6が形成され(第2図(d))、該開口6から不純物が
拡散されてエミッタ領域7が形成される。 エミッタ領
域7の拡散工程中にもエミッタ領域7上に酸化膜8が成
長するので、酸化膜5と酸化膜8とに再び段差が形成さ
れる(第2図(e))。 そこで、電極用の開口を穿設
するには、まず、熱酸化膜1と酸化膜5.8とにホトレ
ジストを塗布し、熱酸化膜1の表面にホトマスクを接触
させ、続いて、露光によりホトレジスト膜にホトマスク
パターンを転写する。 ポストベークの後、ホトレジス
ト膜のパターン形成がなされ、このパターン形成された
ホトレジスト膜をマスクとして酸化膜5,8に開口9,
10が穿設される(第2図(f))。<Prior Art> FIGS. 2(a) to 2(f) are process diagrams showing a conventional example, and FIG. 2(a) shows a semiconductor substrate 2 on which a thermal oxide film 1 has been grown. An opening 3 is formed in the thermal oxide film 1 through a lithography process (FIG. 2(b)), and impurities are diffused through the opening 3 to form a base region 4. During the diffusion process, an oxide film 5 is grown on the base region 4, and a step is formed between the thermal oxide film 1 and the oxide film 5 (see FIG. 2).
C)). Subsequently, an opening 6 for emitter diffusion is formed in the oxide film 5 (FIG. 2(d)), and impurities are diffused through the opening 6 to form an emitter region 7. Since the oxide film 8 grows on the emitter region 7 during the diffusion process of the emitter region 7, a step is again formed between the oxide film 5 and the oxide film 8 (FIG. 2(e)). Therefore, in order to form openings for electrodes, first, photoresist is applied to the thermal oxide film 1 and the oxide film 5.8, a photomask is brought into contact with the surface of the thermal oxide film 1, and then the photoresist is formed by exposure. Transfer the photomask pattern onto the membrane. After post-baking, the photoresist film is patterned, and openings 9, 8 are formed in the oxide films 5 and 8 using the patterned photoresist film as a mask.
10 is drilled (FIG. 2(f)).
〈発明の解決しようとする問題点〉
上記従来例にあっては、熱酸化膜1と酸化膜5と8との
間に、段差がそれぞれ形成されていたので、開口9,1
0の穿設の際、熱酸化膜1の表面に当てられたホトマス
クから酸化膜5と8とまでの距離が異なるようになる。<Problems to be Solved by the Invention> In the above conventional example, since steps were formed between the thermal oxide film 1 and the oxide films 5 and 8, the openings 9 and 1
0, the distances from the photomask applied to the surface of the thermal oxide film 1 to the oxide films 5 and 8 become different.
一般に、照射される光の波長をλとし、ホトマスクと
ホトレジスト膜との間隔をGとすると、解像度Rは、G
とλとの積の平方根に比例する。 したがって、開口9
の寸法精度と開口10の寸法精度とに差ができることに
加え、酸化膜5と8との膜厚に差があり。Generally, if the wavelength of the irradiated light is λ and the distance between the photomask and the photoresist film is G, then the resolution R is G
is proportional to the square root of the product of and λ. Therefore, the aperture 9
In addition to there being a difference in the dimensional accuracy of the opening 10 and the dimensional accuracy of the opening 10, there is also a difference in the thickness of the oxide films 5 and 8.
酸化膜8がオーバーエツチングされることから。This is because the oxide film 8 is over-etched.
開口9,10の寸法が不所望の値になりがちである。
そのため、解像度の観点より関口9.10さらには、オ
ーバーエツチングの観点よりベース領域4、エミッタ領
域7は大きく形成しなければならないという問題点があ
った。The dimensions of the openings 9, 10 tend to be undesirable values.
Therefore, from the viewpoint of resolution, the base region 4 and the emitter region 7 had to be formed large, which was problematic because of the need for overetching.
く問題点を解決するための手段〉〉
本発明は上記問題点に鑑み、第1導電型の不純物を導入
後、半導体基板の表面に酸化膜を形成し、該酸化膜をマ
スクとして第2導電型の不純物領域を形成すると共に、
この酸化膜を除去することなく、該酸化膜に開口を穿設
し、第2導電型の不純物導入に使用した関口と新たに穿
設した開口とにそれぞれ電極を形成するようにしたこと
を要旨とする。A means for solving problems>> In light of the above problems, after introducing the first conductive impurities, the oxide film is formed on the surface of the semiconductor substrate, and the oxide film is the second conductor. While forming the impurity region of the mold,
Summary: Without removing this oxide film, openings were drilled in the oxide film, and electrodes were formed at the Sekiguchi used to introduce the second conductivity type impurity and at the newly drilled openings. shall be.
〈実施例〉
第1図(a)乃至(h)は本発明の一実施例を表わして
おり、図中、11はN型の半導体基板を示しており、半
導体基板11の表面には、厚さ約1000人の二酸化シ
リコン膜12が成長させられている(第1図(a))、
二酸化シリコン膜12上には、ホトレジスト13が
塗布され、パターン形成後、不純物ドーズ置駒10”i
o n s/13のP型の不純物1例えばボロンが半
導体基板11にイオン打ち込みされる(第1図(b))
。<Embodiment> FIGS. 1(a) to 1(h) show an embodiment of the present invention, in which numeral 11 indicates an N-type semiconductor substrate, and the surface of the semiconductor substrate 11 has a Approximately 1000 silicon dioxide films 12 are grown (FIG. 1(a)).
A photoresist 13 is coated on the silicon dioxide film 12, and after patterning, an impurity dose setting piece 10''i is applied.
On s/13 P-type impurity 1, such as boron, is ion-implanted into the semiconductor substrate 11 (FIG. 1(b)).
.
ホトレジスト膜の除去後、二酸化シリコン膜12上に二
酸化シリコン膜14がCVD法により約1500人の厚
さに被着され(第1図(Q))。After removing the photoresist film, a silicon dioxide film 14 is deposited on the silicon dioxide film 12 to a thickness of about 1,500 mm by CVD (FIG. 1(Q)).
約900℃乃至1000℃の熱処理工程を経てベース領
域15が形成される(第1図(d))。A base region 15 is formed through a heat treatment process at approximately 900° C. to 1000° C. (FIG. 1(d)).
続く工程では、二酸化シリコン膜14に関口16が穿設
され、ベース領域15が露出される。In the subsequent step, a gate 16 is formed in the silicon dioxide film 14 and the base region 15 is exposed.
この開口16の穿設工程では、二酸化シリコン膜14に
ホトレジストが塗布された後、ホトレジスト膜は密着露
光方式でパターン形成されるので。In the step of forming the opening 16, after the silicon dioxide film 14 is coated with photoresist, the photoresist film is patterned by a contact exposure method.
ホトマスクのパターンはホトレジスト膜に正確に転写さ
れ、所望寸法の関口16が穿設できる。The pattern of the photomask is accurately transferred to the photoresist film, and a gate 16 of a desired size can be formed.
ベース領域15が露出されると、該露出されたベース領
域15と二酸化シリコン膜14とにN型の不純物、例え
ばリンを含んだ約500乃至1000人のポリシリコン
膜17が被着され、その上にキャップオキサイド膜が形
成される(第1図(e))。 キャップオキサイド膜の
形成後、熱処理によりポリシリコン膜17から半導体基
板11にリンが拡散し、N型のエミッタ領域18が形成
される。 この後、キャップオキサイド膜が全面エツチ
ング除去され、ポリシリコン1i17はエミッタ領域1
8上を除いてエツチングされる(第1図(f))。Once the base region 15 is exposed, a polysilicon film 17 of about 500 to 1000 layers containing an N-type impurity, for example, phosphorus, is deposited on the exposed base region 15 and the silicon dioxide film 14. A cap oxide film is formed on the surface (FIG. 1(e)). After the cap oxide film is formed, phosphorus is diffused from the polysilicon film 17 into the semiconductor substrate 11 by heat treatment, and an N-type emitter region 18 is formed. After this, the cap oxide film is removed by etching the entire surface, and the polysilicon 1i17 is removed from the emitter region 1.
It is etched except for the top part 8 (FIG. 1(f)).
続いて、ベース領域15上の二酸化シリコン膜14にベ
ース電極用の開口19.20が穿設される(第1図(g
))。 開口19.20の穿設にあっては、二酸化シリ
コン膜14の表面が平坦なので、ホトマスクを該表面に
略密着させることができ、所望寸法の開口19.20を
形成することができる。 したがって、二酸化シリコン
膜14と露出されたベース領域15とポリシリコン膜1
7とを被って金属、例えばアルミニウムを蒸着し。Subsequently, openings 19 and 20 for base electrodes are formed in the silicon dioxide film 14 on the base region 15 (see FIG. 1(g)).
)). In forming the openings 19.20, since the surface of the silicon dioxide film 14 is flat, the photomask can be brought into substantially close contact with the surface, and the openings 19.20 of desired dimensions can be formed. Therefore, the silicon dioxide film 14, the exposed base region 15 and the polysilicon film 1
7 and evaporate a metal, for example, aluminum.
これをパターン形成してベース電極21とエミッタ電極
22とが形成される(第1図(h))。By patterning this, a base electrode 21 and an emitter electrode 22 are formed (FIG. 1(h)).
この際、ベース電極21とエミッタ電極22は略同一平
面にあり、電極形成用のホトマスク工程においても、開
口19,20の穿設におけると同様なことがいえる。At this time, the base electrode 21 and the emitter electrode 22 are on substantially the same plane, and the same can be said for the photomask process for forming the electrodes as for forming the openings 19 and 20.
〈効果〉
以上説明してきたように1本発明によれば、第2導電型
の不純物領域形成用の開口が形成された酸化膜を除去す
ることなく、該酸化膜に第1導電型の不純物領域を露出
させる開口を設け、該開口と第2導電型の不純物領域形
成用の開口とに電極を設けたので、いずれの開口の穿設
も密着露光方式でパターン形成することができ、開口を
所望の寸法に正確に形成できるという効果が得られる。<Effects> As described above, according to the present invention, the impurity region of the first conductivity type is formed in the oxide film without removing the oxide film in which the opening for forming the impurity region of the second conductivity type is formed. An opening is provided to expose the impurity region, and an electrode is provided in the opening and the opening for forming the second conductivity type impurity region. Therefore, both openings can be patterned using a contact exposure method, and the opening can be formed as desired. The effect is that it can be formed accurately to the dimensions of .
しかも、電極の形成される開口の寸法を精密に制御でき
るので、第1導電型の不純物領域と第2導電型の不純物
領域とを縮小することができ、集積度の向上、さらには
、トランジスタの特性の改善を図ることができるという
効果が得られる。Moreover, since the dimensions of the openings in which the electrodes are formed can be precisely controlled, the impurity regions of the first conductivity type and the impurity regions of the second conductivity type can be reduced, which improves the degree of integration and further improves the efficiency of transistors. The effect is that the characteristics can be improved.
第1図(a)乃至(h)は本発明の一実施例の工程図、
第2図(a)乃至(f)は従来例の工程図である。
11・・・・・・・半導体基板、
13・・・・・・・マスク層、
14・・・・・・・酸化膜。
15・・・・・・・第1導電型の不純物領域、16.1
9.20・開口、
18・・・・・・・第2導電型の不純物領域。
21.22・・・・電極。
特許出願人 ローム株式会社代理人 弁
理士 桑 井 清 −(e!4)
(C)
(d )
第1図
(11’)
第1図
C=3 )
(b)
第2図
今
((1’)
(e )
第2図FIGS. 1(a) to (h) are process diagrams of an embodiment of the present invention,
FIGS. 2(a) to 2(f) are process diagrams of a conventional example. 11... Semiconductor substrate, 13... Mask layer, 14... Oxide film. 15... First conductivity type impurity region, 16.1
9.20・Opening, 18・・・・Impurity region of second conductivity type. 21.22... Electrode. Patent Applicant ROHM Co., Ltd. Representative Patent Attorney Kiyoshi Kuwai - (e!4) (C) (d) Figure 1 (11') Figure 1 C=3) (b) Figure 2 Now ((1') ) (e) Figure 2
Claims (1)
電型の不純物を導入する工程と、マスク層を除去して半
導体基板の表面に酸化膜を形成する工程と、該酸化膜に
開口を設け該開口から半導体基板の表面に不純物を導入
して第1導電型の不純物領域内に第2導電型の不純物領
域を形成する工程と、前記酸化膜に開口を設け第1導電
型の不純物領域を露出させる工程と、前記第1導電型の
不純物領域上と第2導電型の不純物領域上との酸化膜に
穿設された開口にそれぞれ電極を設け該電極を第1導電
型の不純物領域と第2導電型の不純物領域とにそれぞれ
接続する工程とから成る微細電極の形成方法。A step of introducing impurities of a first conductivity type through a mask layer formed on the surface of the semiconductor substrate, a step of removing the mask layer to form an oxide film on the surface of the semiconductor substrate, and forming an opening in the oxide film. introducing an impurity into the surface of the semiconductor substrate through the opening to form an impurity region of a second conductivity type within the impurity region of the first conductivity type; and forming an opening in the oxide film to form an impurity region of the first conductivity type. exposing the impurity region of the first conductivity type and the impurity region of the second conductivity type; A method for forming a microelectrode comprising the step of connecting to impurity regions of two conductivity types.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60148330A JP2564113B2 (en) | 1985-07-08 | 1985-07-08 | Method for forming fine electrodes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60148330A JP2564113B2 (en) | 1985-07-08 | 1985-07-08 | Method for forming fine electrodes |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS629625A true JPS629625A (en) | 1987-01-17 |
JP2564113B2 JP2564113B2 (en) | 1996-12-18 |
Family
ID=15450362
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60148330A Expired - Lifetime JP2564113B2 (en) | 1985-07-08 | 1985-07-08 | Method for forming fine electrodes |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2564113B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5546539A (en) * | 1978-09-27 | 1980-04-01 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
-
1985
- 1985-07-08 JP JP60148330A patent/JP2564113B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5546539A (en) * | 1978-09-27 | 1980-04-01 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2564113B2 (en) | 1996-12-18 |
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