JP2564113B2 - Method for forming fine electrodes - Google Patents

Method for forming fine electrodes

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Publication number
JP2564113B2
JP2564113B2 JP60148330A JP14833085A JP2564113B2 JP 2564113 B2 JP2564113 B2 JP 2564113B2 JP 60148330 A JP60148330 A JP 60148330A JP 14833085 A JP14833085 A JP 14833085A JP 2564113 B2 JP2564113 B2 JP 2564113B2
Authority
JP
Japan
Prior art keywords
oxide film
conductivity type
opening
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60148330A
Other languages
Japanese (ja)
Other versions
JPS629625A (en
Inventor
和文 三本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP60148330A priority Critical patent/JP2564113B2/en
Publication of JPS629625A publication Critical patent/JPS629625A/en
Application granted granted Critical
Publication of JP2564113B2 publication Critical patent/JP2564113B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 <産業上の利用分野> 本発明は微細電極の形成方法に係わり、特にPN接合の
形成後、各領域に接続される電極を所定寸法に精度よく
穿設できる微細電極の形成方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method for forming a fine electrode, and in particular, after forming a PN junction, a fine electrode capable of accurately forming electrodes connected to respective regions with a predetermined size. And a method of forming the same.

<従来の技術> 第2図(a)乃至(f)は従来例を表わす工程図であ
り、第2図(a)は熱酸化膜1の成長した半導体基板2
を表わしている。熱酸化膜1はリソグラフィー工程を経
て開口3が穿設され(第2図(b))、該開口3から不
純物が拡散されてベース領域4が形成される。拡散工程
中にベース領域4上には酸化膜5が成長され、熱酸化膜
1と酸化膜5との間には段差が形成される(第2図
(c))。続いて、酸化膜5にはエミッタ拡散用の開口
6が形成され(第2図(d))、該開口6から不純物が
拡散されてエミッタ領域7が形成される。エミッタ領域
7の拡散工程中にもエミッタ領域7上に酸化膜8が成長
するので、酸化膜5と酸化膜8とに再び段差が形成され
る(第2図(e))。そこで、電極用の開口を穿設する
には、まず、熱酸化膜1と酸化膜5,8とにホトレジスト
を塗布し、熱酸化膜1の表面にホトマスクを接触させ、
続いて、露光によりホトレジスト膜にホトマスクパター
ンを転写する。ポストベークの後、ホトレジスト膜のパ
ターン形成がなされ、このパターン形成されたホトレジ
ス膜をマスクとして酸化膜5,8に開口9,10が穿設される
(第2図(f))。
<Prior Art> FIGS. 2A to 2F are process diagrams showing a conventional example, and FIG. 2A is a semiconductor substrate 2 on which a thermal oxide film 1 is grown.
Is represented. An opening 3 is formed in the thermal oxide film 1 through a lithography process (FIG. 2B), and impurities are diffused from the opening 3 to form a base region 4. An oxide film 5 is grown on the base region 4 during the diffusion process, and a step is formed between the thermal oxide film 1 and the oxide film 5 (FIG. 2 (c)). Subsequently, an emitter diffusion opening 6 is formed in the oxide film 5 (FIG. 2 (d)), and impurities are diffused from the opening 6 to form an emitter region 7. Since the oxide film 8 grows on the emitter region 7 even during the diffusion process of the emitter region 7, a step is again formed between the oxide film 5 and the oxide film 8 (FIG. 2 (e)). Therefore, in order to form an opening for an electrode, first, a photoresist is applied to the thermal oxide film 1 and the oxide films 5 and 8, and a photomask is brought into contact with the surface of the thermal oxide film 1.
Then, the photomask pattern is transferred to the photoresist film by exposure. After the post-baking, the photoresist film is patterned, and openings 9 and 10 are formed in the oxide films 5 and 8 by using the patterned photoresist film as a mask (FIG. 2 (f)).

<発明の解決しようとする問題点> 上記従来例にあっては、熱酸化膜1と酸化膜5と8と
の間に、段差がそれぞれ形成されていたので、開口9,10
の穿設の際、熱酸化膜1の表面に当てられたホトマスク
から酸化膜5と8とまでの距離が異なるようになる。一
般に、照射される光の波長をλとし、ホトマスクとホト
レジスト膜との間隔をGとすると、解像度Rは、Gとλ
との積の平方根に比例する。したがって、開口9と寸法
精度と開口10の寸法精度とに差ができることに加え、酸
化膜5と8との膜厚に差があり、酸化膜8がオーバーエ
ッチングされることから、開口9,10の寸法が不所望の値
になりがちである。そのため、解像度の観点より開口9,
10さらには、オーバーエッチングの観点よりベース領域
4、エミッタ領域7は大きく形成しなければならないと
いう問題点があった。
<Problems to be Solved by the Invention> In the above-mentioned conventional example, the steps 9 and 10 are formed between the thermal oxide film 1 and the oxide films 5 and 8, respectively.
At the time of drilling, the distance from the photomask applied to the surface of the thermal oxide film 1 to the oxide films 5 and 8 becomes different. Generally, if the wavelength of the irradiated light is λ and the distance between the photomask and the photoresist film is G, the resolution R is G and λ.
Proportional to the square root of the product of and. Therefore, in addition to the dimensional accuracy of the opening 9 and the dimensional accuracy of the opening 10, there is a difference in film thickness between the oxide films 5 and 8, and the oxide film 8 is over-etched. The dimensions tend to have undesired values. Therefore, from the perspective of resolution 9,
Furthermore, from the viewpoint of over-etching, the base region 4 and the emitter region 7 must be formed large.

<問題点を解決するための手段> 本発明は上記問題点に鑑み、半導体基板の表面に酸化
膜を形成し、第1導電型の不純物を導入後、半導体基板
の表面に酸化膜をCVD法を用いて形成し、該酸化膜をマ
スクとして第2導電型の不純物領域を形成すると共に、
この酸化膜を除去することなく、該酸化膜に開口を穿設
し、第2導電型の不純物導入に使用した開口と新たに穿
設した開口とにそれぞれ電極を形成するようにしたこと
を要旨とする。
<Means for Solving Problems> In view of the above problems, the present invention forms an oxide film on the surface of a semiconductor substrate, introduces impurities of the first conductivity type, and then forms the oxide film on the surface of the semiconductor substrate by a CVD method. And using the oxide film as a mask to form a second conductivity type impurity region,
An opening is formed in the oxide film without removing the oxide film, and electrodes are respectively formed in the opening used for introducing the second conductivity type impurities and the newly formed opening. And

<実施例> 第1図(a)乃至(h)は本発明の一実施例を表わし
ており、図中、11はN型の半導体基板を示しており、半
導体基板11の表面には、厚さ約1000Åの二酸化シリコン
膜12が成長させられている(第1図(a))。二酸化シ
リコン膜12上には、ホトレジスト13が塗布され、パター
ン形成後、不純物ドーズ量約1014ions/cm3のP型の不純
物、例えばボロンが半導体基板11にイオン打ち込みされ
る(第1図(b))。
<Embodiment> FIGS. 1A to 1H show an embodiment of the present invention, in which 11 denotes an N-type semiconductor substrate, and the surface of the semiconductor substrate 11 has a thickness of A silicon dioxide film 12 having a thickness of about 1000Å is grown (Fig. 1 (a)). A photoresist 13 is applied on the silicon dioxide film 12, and after patterning, a P-type impurity with an impurity dose amount of about 10 14 ions / cm 3 , for example, boron is ion-implanted into the semiconductor substrate 11 (see FIG. b)).

ホトレジスト膜の除去後、二酸化シリコン膜12上に二
酸化シリコン膜14がCVD法により約1500Åの厚さに被着
され(第1図(c))、約900℃乃至1000℃の熱処理工
程を経てベース領域15が形成される(第1図(d))。
After removing the photoresist film, a silicon dioxide film 14 is deposited on the silicon dioxide film 12 by the CVD method to a thickness of about 1500 Å (Fig. 1 (c)), and a heat treatment process at about 900 ° C to 1000 ° C is performed to form a base A region 15 is formed (Fig. 1 (d)).

続く工程では、二酸化シリコン膜14に開口16が穿設さ
れ、ベース領域15が露出される。この開口16の穿設工程
では、二酸化シリコン膜14にホトレジスが塗布された
後、ホトレジスト膜は密着露光方式でパターン形成され
るので、ホトマスクのパターンはホトレジスト膜に正確
に転写され、所望寸法の開口16が穿設できる。
In the subsequent step, the opening 16 is formed in the silicon dioxide film 14 and the base region 15 is exposed. In the step of forming the opening 16, since the photoresist film is applied to the silicon dioxide film 14 and then the photoresist film is patterned by the contact exposure method, the pattern of the photoresist is accurately transferred to the photoresist film, and the opening of the desired size is formed. 16 can be drilled.

ベース領域15が露出されると、該露出されたベース領
域と二酸化シリコン膜14とにN型の不純物、例えばリン
を含んだ約500乃至1000Åのポリシリコン膜17が被着さ
れ、その上にキャップオキサイド膜が形成される(第1
図(e))。キャップオキサイド膜の形成後、熱処理に
よりポリシリコン膜17から半導体基板11にリンが拡散
し、N型エミッタ領域18が形成される。この後、キャッ
プオキサイド膜が全面エッチング除去され、ポリシリコ
ン膜17はエミッタ領域18上を除いてエッチングされる
(第1図(f))。
When the base region 15 is exposed, a polysilicon film 17 of about 500 to 1000 Å containing N-type impurities such as phosphorus is deposited on the exposed base region and the silicon dioxide film 14, and a cap is formed thereon. An oxide film is formed (first
Figure (e)). After the formation of the cap oxide film, phosphorus is diffused from the polysilicon film 17 into the semiconductor substrate 11 by heat treatment to form the N-type emitter region 18. After that, the cap oxide film is entirely removed by etching, and the polysilicon film 17 is etched except on the emitter region 18 (FIG. 1 (f)).

続いて、ベース領域15上の二酸化シリコン膜14にベー
ス電極用の開口19,20が穿設される(第1図(g))。
開口19,20の穿設にあっては、二酸化シリコン膜14の表
面が平坦なので、ホトマスクを該表面に略密着させるこ
とができ、所望寸法の開口19,20を形成することができ
る。したがって、二酸化シリコン膜14と露出されたベー
ス領域15とポリシリコン膜17とを被って金属、例えばア
ルミニウムを蒸着し、これをパターン形成してベース電
極21とエミッタ電極22とが形成される(第1図
(h))。この際、ベース電極21とエミッタ電極22は略
同一平面にあり、電極形成用のホトマスク工程において
も、開口19,20の穿設におけると同様なことがいえる。
Then, openings 19 and 20 for base electrodes are formed in the silicon dioxide film 14 on the base region 15 (FIG. 1 (g)).
In forming the openings 19 and 20, since the surface of the silicon dioxide film 14 is flat, the photomask can be brought into close contact with the surface, and the openings 19 and 20 having desired dimensions can be formed. Therefore, a metal, for example, aluminum is vapor-deposited on the silicon dioxide film 14, the exposed base region 15 and the polysilicon film 17, and this is patterned to form the base electrode 21 and the emitter electrode 22 (first Figure 1 (h)). At this time, the base electrode 21 and the emitter electrode 22 are substantially on the same plane, and it can be said that the same applies to the formation of the openings 19 and 20 in the photomask process for forming the electrodes.

<効果> 以上説明してきたように、本発明によれば、第2導電
型の不純物領域形成用の開口が形成された酸化膜を除去
することなく、該酸化膜に第1導電型の不純物領域を露
出させる開口を設け、該開口と第2導電型の不純物領域
形成用の開口とに電極を設けたので、いずれの開口の穿
設も密着露光方式でパターン形成することができ、開口
を所望の寸法に正確に形成できるという効果が得られ
る。しかも、電極の形成される開口の寸法を精密に制御
できるので、第1導電型の不純物領域と第2導電型の不
純物領域とを縮小することができ、集積度の向上、さら
には、トランジスタの特性の改善を図ることができると
いう効果が得られる。
<Effect> As described above, according to the present invention, the first conductivity type impurity region is formed in the oxide film without removing the oxide film in which the opening for forming the second conductivity type impurity region is formed. Since the openings for exposing the holes are provided, and the electrodes are provided in the openings and the openings for forming the impurity regions of the second conductivity type, it is possible to form a pattern by the contact exposure method for forming any of the openings. It is possible to obtain an effect that it can be accurately formed in the dimension of. Moreover, since the size of the opening in which the electrode is formed can be precisely controlled, the first conductivity type impurity region and the second conductivity type impurity region can be reduced, and the integration degree can be improved, and further, the transistor The effect that the characteristics can be improved can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)乃至(h)は本発明の一実施例の工程図、
第2図(a)乃至(f)は従来例の工程図である。 11……半導体基板、 13……マスク層、 14……酸化膜、 15……第1導電型の不純物領域、 16,19,20……開口、 18……第2導電型の不純物領域、 21,22……電極。
1 (a) to (h) are process diagrams of an embodiment of the present invention,
2A to 2F are process diagrams of a conventional example. 11 ... Semiconductor substrate, 13 ... Mask layer, 14 ... Oxide film, 15 ... First conductivity type impurity region, 16, 19, 20 ... Opening, 18 ... Second conductivity type impurity region, 21 , 22 …… Electrode.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板の表面に酸化膜を形成する工程
と、 該酸化膜の表面上に形成されたマスク層により第1導電
型の不純物を前記半導体基板に導入する工程と、 マスク層を除去して前記酸化膜の表面にさらに酸化膜を
CVD法を用いて形成する工程と、 該酸化膜表面に開口を設け該開口から半導体基板の表面
に不純物を導入して第1導電型の不純物領域内に第2導
電型の不純物領域を形成する工程と、 前記酸化膜に開口を設け第1導電型の不純物領域を露出
させる工程と、 前記第1導電型の不純物領域上と第2導電型の不純物領
域上との酸化膜に穿設された開口にそれぞれ電極を設け
該電極を第1導電型の不純物領域と第2導電型の不純物
領域とにそれぞれ接続する工程とから成る微細電極の形
成方法。
1. A step of forming an oxide film on the surface of a semiconductor substrate, a step of introducing impurities of a first conductivity type into the semiconductor substrate by a mask layer formed on the surface of the oxide film, and a mask layer To remove the oxide film on the surface of the oxide film.
A step of forming using a CVD method, and forming an opening in the surface of the oxide film to introduce impurities into the surface of the semiconductor substrate through the opening to form an impurity region of the second conductivity type in the impurity region of the first conductivity type. A step of forming an opening in the oxide film to expose an impurity region of the first conductivity type; and a step of forming an oxide film on the impurity region of the first conductivity type and the impurity region of the second conductivity type. A method of forming a fine electrode, comprising a step of providing an electrode in each opening and connecting the electrode to an impurity region of a first conductivity type and an impurity region of a second conductivity type, respectively.
JP60148330A 1985-07-08 1985-07-08 Method for forming fine electrodes Expired - Lifetime JP2564113B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60148330A JP2564113B2 (en) 1985-07-08 1985-07-08 Method for forming fine electrodes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60148330A JP2564113B2 (en) 1985-07-08 1985-07-08 Method for forming fine electrodes

Publications (2)

Publication Number Publication Date
JPS629625A JPS629625A (en) 1987-01-17
JP2564113B2 true JP2564113B2 (en) 1996-12-18

Family

ID=15450362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60148330A Expired - Lifetime JP2564113B2 (en) 1985-07-08 1985-07-08 Method for forming fine electrodes

Country Status (1)

Country Link
JP (1) JP2564113B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546539A (en) * 1978-09-27 1980-04-01 Mitsubishi Electric Corp Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS629625A (en) 1987-01-17

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