JPS6278871A - Forming method for wiring of complementary mos transistor - Google Patents

Abstract

PURPOSE:To obtain an excellent ohmic contact in a wiring by providing apertures on an insulating film covering gate electrodes and source.drain regions of the same conduction type as the gate electrodes, and forming the wiring after introducing impurity from the apertures. CONSTITUTION:A field oxide film 11 and a gate oxide film 12 are grown after an N-type well 10 is formed on a P-type silicon substrate 1, and then gate electrodes 3 are formed on a gate oxide film 12. Successively, an N-type source.drain region 6 and a P-type source.drain region 5 are formed in order on a substrate 1 and a well 10, and an inter-layer insulating film 4 is stuck by CVD method. Contact holes 13 are made on the inter-layer insulating film 4 on the gate electrode 3 and the N-type source.drain region 6. After the ion implantation of N-type impurity, annealing at the temperature of 960 deg.C is performed for about 20min. Then a contact hole is made on the insulating layer 4 on the P-type source.drain region 5 to form the wiring by Al, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming wiring for complementary MOS transistors, and more particularly, to a method for forming wiring for complementary MOS transistors including gates of semiconductors containing impurities.

[Prior art]

In recent years, as the degree of integration of semiconductor devices has improved, the line width of interconnects has also decreased, increasing interconnect resistance and causing problems with signal propagation delays. Attempts have been made to reduce wiring resistance by using so-called polycide, which is a layered layer of silicon. A complementary MOS transistor (hereinafter referred to as CMO8) in which interconnections and gate electrodes are formed using polycide is manufactured by forming an oxide film 2 on a semiconductor substrate 1, as shown in FIG. 2, and forming a polycide gate on the oxide film. After forming the electrode 3, source/drain regions 5 and 6 are formed in the substrate and well, respectively, and covered with an oxide film 4. A contact hole 7 is regularly formed in the oxide film 4 on the source/drain region of the substrate and in the well, and in the oxide film 4 on the gate electrode, and wiring is formed using aluminum or the like through the contact hole 7. was.

However, since the source/drain regions 5, 6, etc. are formed after forming the gate electrode, impurities evaporate from the polycide of the gate electrode 3, resulting in good ohmic and
Because it is not possible to obtain contact with wires, there have been requests to increase the concentration of impurities in gate electrodes and the like before wiring.

After forming the contact hole 7 in a solitary process, an organic resist is applied to the entire surface, and an opening is made again in the contact hole of the gate electrode and the source/drain region of the same conductivity type.
Ion implantation was used to increase the impurity concentration in gate electrodes, etc.

[Problem to be solved by the invention]

However, in the highly integrated CMO8, the source/drain regions of each element are extremely fine, and providing openings for ion implantation there requires accurate drilling, taking into account photomask alignment errors. However, if the source/drain regions are enlarged in consideration of errors, the degree of integration decreases. Furthermore, s lXl07c
If an attempt is made to perform ion implantation of m or more, there is a problem in that the organic resist changes in quality and has an adverse effect on the semiconductor substrate.

[Means for solving problems]

In the present invention, an opening is formed in an insulating film above a gate electrode and a source/drain region of the same conductivity, and then impurities are introduced to increase the impurity concentration, and then the gate electrode is of a conductivity type opposite to that of the gate electrode. The gist of this method is to provide an opening in the insulating film over the source/drain region and form wiring.

〔Example〕

FIG. 1 is a sectional view showing an intermediate step in an embodiment of the present invention. After forming an n-type well 10 on a p-type silicon substrate 1, a field oxide film 11 of about 1 μm and a gate oxide film of about 50 OA are formed. The film 12 is grown. On the gate oxide film 12, polysilicon with n-type impurities diffused therein and a high melting point metal silicide such as titanium silicide, molybdenum silicide, etc. are laminated, and the gate electrode 3 is formed by patterning. Next, an n-type source/drain region 6 and a p-type source/drain region 5 are formed with a thickness of 0.6 μm on the substrate 1 and the well 1o.
The interlayer insulating film 4 is formed by forming a second shadow at a depth of 0.0.
Deposit 7 μm.

After that, the gate electrode 3 and the n-type source/drain region 6
A contact hole 13 is formed in the interlayer insulating film 4 above the p-type source/drain region 5, but no contact hole is formed in the insulating film 4 above the p-type source/drain region 5.

FIG. 1 shows this state. 4
Next, an n-type impurity, for example, phosphorus, is ion-implanted at an energy of 80 keV to approximately 2.5XIO/cm2.
Annealing is performed at 960° C. for about 20 minutes.

Next, contact holes are formed in the insulating film 4 on the p-type source/drain regions 5, and wiring is formed using aluminum or the like.

〔effect〕

As described above, according to the present invention, an opening is provided in the insulating film over the gate electrode and the source/drain regions of the same conductivity type, and after introducing impurities through the opening, Openings are made in the insulating film over the source/drain regions to form wiring, which not only allows for good ohmic contact with the wiring, but also helps protect the source/drain regions of opposite conductivity type when introducing impurities. Since there is no need to apply a resist, the semiconductor substrate is not adversely affected by the resist during the introduction of impurities.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an intermediate step in an embodiment of the present invention, and FIG. 2 is a sectional view showing a step corresponding to FIG. 1 in a conventional example. l... Semiconductor substrate, 3... Gate, 4
...Insulating film, 5...First conductivity type source/drain region, 6...Second conductivity type source/drain region, 10... Well, 13...
...Openings drilled in the insulating film over the source/drain regions of the same conductivity type as the gate and gate (Figure 2)

Claims (1)

[Claims] A source/drain region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a source/drain region of a first conductivity type formed in a well of a second conductivity type in the semiconductor substrate; an insulating film covering the surface of the insulating film, a channel between the source and drain of the first conductivity type, a channel between the source and drain of the second conductivity type, and a channel between the source and drain of the second conductivity type through the insulating film. In a method for forming wiring of a complementary MOS transistor having a gate including a semiconductor of a first or second conductivity type facing each other, and an insulating film covering the gate, an insulating film on the gate and a source of the same conductivity type as the gate. - a step of drilling an opening in the insulating film over the drain region, and a step of introducing impurities through the opening to increase the impurity concentration of the gate and source/drain regions;
A method for forming wiring for a coarsely complementary MOS transistor, including the steps of: forming an opening in a source/drain region of a conductivity type opposite to that of the gate; and forming a wiring through the opening.