JP2945069B2 - Connection structure of different polarity conductive layers - Google Patents

Description

The present invention is applied to a connection structure of conductive layers having different polarities, which is applicable to a semiconductor device.

(Prior Art) Conventionally, in a semiconductor device, it may be necessary to connect conductive layers having different polarities to each other. Hereinafter, for example, a conventional connection structure of conductive layers of different polarities will be described for the case of a CMOS IC.

2 (A) and 2 (B) are views for explaining a conventional connection structure, and are plan views showing main parts of a CMOS semiconductor device disclosed in JP-A-59-4067. II-II
It is sectional drawing corresponding to the part shown along the line.
This conventional semiconductor device has an N-channel MOS transistor T
_{An N-} type polysilicon gate 10n is formed on _N , and a P-channel
By forming the P-type silicon gate 10p the NOS transistor T _P, and has a structure capable of preventing a decrease in the absolute value of the drop and the threshold voltage of the punch-through breakdown voltage in the miniaturization of P-channel MOS transistor T _P.

The N-type (n ⁺ ) and P-type (p ⁺ ) polysilicon gates 10n and 10p are connected to a common polysilicon layer.
Ions (n ⁺ : arsenic (As) ions, P ⁺ : boron (B) ions) which determine the conductivity type are implanted to form adjacent regions.

In the illustrated embodiment, this boundary is provided on the field oxide film 26. In addition, both of these polysilicon gates 10
Of the regions n and 10p, a part of the region away from the activation regions 12n and 12p where the source and drain diffusion layers are formed, respectively, It is formed as a metal silicide region 14 for establishing an ohmic contact to achieve electrical coupling between both polysilicon gates 10n and 10p. 2 (A) and 2 (B), reference numeral 20 denotes an N-type substrate, 22 denotes a P well, 24 denotes a gate oxide film, 26 denotes a field oxide film, 28n denotes an N channel, and 28p denotes a P channel.
Channels, 30n and 30p are channel cut diffusion layers, 32 is an oxide film, 34 is a PSG (phosphosilicate) glass film, 36 is an aluminum electrode, 38 is a contact hole for an aluminum electrode, 40 is a PSG film, 42 is a source or This is a contact hole for the drain diffusion layer.

(Problems to be Solved by the Invention) However, in the above-described conventional structure, the metal silicide region is in contact with n ⁺ polysilicon in one half, and is in contact with p ⁺ polysilicon in the other half. Of polysilicon is directly bonded. Normally, n ⁺ polysilicon is formed by implanting As ions as impurity ions into the polysilicon layer, and therefore, the n ⁺ polysilicon contains As ions. Further, metal silicide usually has a large diffusion coefficient for As ions.

On the other hand, after the formation of the metal silicide region 14, in the stage of the manufacturing process of the CMOS semiconductor device, a heat treatment is performed at a temperature of about 900 ° C. in order to cover the PSG film 34 and planarize the PSG film. Due to this heat treatment, As ions in the n ⁺ polysilicon gate 10n may diffuse into the metal silicide region 14 and be doped into the P ⁺ polysilicon gate 10p. When As ions diffuse into the interface between the metal silicide region 14 and the P ⁺ polysilicon gate 10p, P ⁺
The hole concentration due to B ions on the surface of the polysilicon gate 10p decreases, and as a result, ohmic failure occurs.

An object of the present invention is to solve the above-described problem of the connection structure of the different polarity conductive layers having the conventional structure,
It is an object of the present invention to provide a connection structure in which an impurity which is noticed in one conductive layer is prevented from diffusing into the other conductive layer.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, a first conductive layer and a second conductive layer made of polysilicon having different conductivity types are provided.
In the connection structure of the conductive layers, a first metal silicide region provided in a part of the first conductive layer and a second metal silicide provided in a part of the second conductive layer in a non-contact state with the first metal silicide region And a third conductive layer that couples the first and second metal silicide regions and has a small diffusion coefficient for impurities that determine the conductivity type of the first or second conductive layer. Features.

In practicing the present invention, preferably, the first
The second conductive layer may be an adjacent region formed by implanting the impurity determining the conductivity type into a common polysilicon layer.

Further, in another preferred embodiment of the present invention, the first and second conductive layers are separate polysilicon layer regions, and these regions are implanted with ions that determine the conductivity type. It is good to form each as a region which is.

Further, in another preferred embodiment of the present invention, the connection between the first and second metal silicide regions and the third conductive layer is preferably performed through a contact hole provided in an insulating layer.

Further, in the practice of the present invention, preferably, the third conductive layer is made of TiN, ZrN, TiB ₂ , ZrB ₂ , TiC and ZrC.
And at least one high-melting point metal compound selected from the group of high-melting point metal compounds.

Further, in the practice of the present invention, preferably, the first and second metal silicide regions include a region made of one kind of metal silicide selected from the group consisting of titanium silicide, zirconium silicide and hafnium silicide. Good to do.

Further, in the practice of the present invention, preferably, when the impurity determining the conductivity type is an N-type conductivity type,
It is good to use As ion.

(Operation) According to the connection structure of the present invention described above, a metal silicide region is provided in a part of each of the first conductive layer and the second conductive layer made of polysilicon, so that ohmic contact with polysilicon is improved. The two metal silicide regions are provided separately from each other, and the two metal silicide regions are joined by a third conductive layer made of a material having a small diffusion coefficient for impurities in polysilicon. Therefore, even if heat treatment is performed in the manufacturing process after the formation of the first and second conductive layers, the metal silicide region, and the third conductive layer, the first
In addition, the impurities in the polysilicon forming the second conductive layer do not diffuse into the third conductive layer, so that no ohmic failure occurs between the first and / or second conductive layer and the metal silicide region.

A high melting point metal compound containing a metal capable of forming a silicide in the third conductive layer, such as TiN, ZrN, TiB ₂ , ZrB ₂ , TiC, ZrC and any other metal compound used in combination. Then, the wiring resistance including the ohmic resistance can be reduced.

Further, when the first and second conductive layers are formed as regions of the conductive layer polysilicon layers which are separate from each other, when the connection structure of the different polarity conductive layers is applied to the gate electrode of the CMOS semiconductor device, Since there is no need to separately provide a contact region for making contact with the external connection aluminum electrode of the gate electrode of the first and second conductive layers, the region of the field oxide film can be reduced by the amount that the contact region is not formed. Therefore, miniaturization of a semiconductor device is possible.

(Example) Hereinafter, an example of a connection structure of a different polarity conductive layer of the present invention will be described with reference to the drawings.

In the drawings shown below, the shapes, sizes, and arrangements of the components are only schematically shown to the extent that the present invention can be understood, and hatchings and the like showing cross-sectional views are omitted except for some parts. I have.

In this embodiment, a case where the connection structure of the present invention is applied to a CMOS semiconductor device will be described as an example.

FIGS. 1 (A) and 1 (B) are a main portion plan view and a cross-sectional view taken along line AA schematically showing the structure of a CMOS semiconductor device used for describing a first embodiment of the present invention. In FIG. 1A, only the main part is taken out and emphasized. The semiconductor device exemplified here also has an N-type polysilicon gate for the conventional N-channel MOS transistor shown in FIGS. 2A and 2B, and a P-type polysilicon gate for the P-channel MOS transistor. 1A and 1B, the components having the same functions as the components shown in FIGS. 2A and 2B are particularly referred to. Unless otherwise noted, the same reference numerals are given and the detailed description thereof is omitted.

In the first embodiment of the connection structure of the present invention, first,
The first conductive layer of polysilicon is formed by a P-channel transistor T _P
Of the P-type (p ⁺⁾ polysilicon gates 50p, to the second conductive layer of polysilicon N type N-channel transistor T _N and (n ⁺⁾ polysilicon gate 50n. These first and second conductive layers 50p and 50n have boron (B) ions as impurities for determining P-type conductivity and arsenic as impurities for determining N-type conductivity in a common polysilicon layer. (As) ions are implanted to form adjacent regions. Further, a first metal silicide region 52 such as titanium silicide, zirconium silicide or hafnium silicide is provided in a part of the first conductive layer 50p, and a first metal silicide region 52 is formed in a part of the second conductive layer 50n. The second metal silicide region 54 is provided using the same material as the metal silicide region. In this case, the first and second metal silicide regions 52 and 54 are regions separated from the activation regions 12p and 12n in which the source / drain diffusion layers are formed, respectively, and are the other conductive layers 50p and 50p, respectively. The portions close to 50n are provided in a non-contact state with each other. Normally, a silicide region is formed on the field oxide film 26 away from the activation region, in order to avoid destruction of the gate oxide film.

An appropriate insulating film such as an oxide film 32 is provided above the first and second conductive layers 50p and 50n.
Contact holes 56 and 58 are formed in portions above the first and second metal silicide regions 52 and 54. In this embodiment, these contact holes
56 and 58 are embedded in a third conductive layer 60 and this third conductive layer
A structure 60 is provided on the insulating film 32 between the contact holes 56 and 58 so as to electrically bridge and connect the respective metal silicide regions 52 and 54. The third conductive layer 60 is formed by using ions that are impurities that determine the conductivity type of the first or second conductive layer 50p or 50n, particularly, for example, arsenic (As) ions that determine the N conductivity type.
Is formed as a conductive layer made of a material having a low diffusion coefficient and low wiring resistance. In this case, the third conductive layer 60,
The combination preferably, the refractory metal nitrides for example TiN, ZrN, refractory metal borides example TiB _2, ZrB _2, and refractory metal carbides for example TiC, layer or these refractory metal compound having a high melting point metal compound such as ZrC, etc. It can be formed as a layer.

Next, a method of forming the connection structure according to the first embodiment of the present invention will be briefly described with reference to an example of a manufacturing process of the CMOS semiconductor device shown in FIGS. 1A and 1B. As in the prior art, a gate oxide film 34 and a field oxide film 26 are formed on the required element regions of the MOS transistors _TP and _TN and the substrate surface on the N-type substrate 20 by using conventional techniques. Thereafter, a polysilicon film is grown, and then polysilicon is patterned in the gate regions of both transistors _TP and _TN . Next, arsenic (As) for T _N is ion-implanted using a suitable mask to form a source /
A drain diffusion layer is formed, and an N-type polysilicon gate (second conductive layer) 50n is formed. Next, the previous mask is removed, and using an appropriate mask, for example, a transistor
To form a P ⁺ source / drain diffusion layer by ion implantation of boron (B) for T _P, to form a P-type polysilicon gate (first conductive layer) 50p.

Next, after removing the latter mask, the whole surface is oxidized, and then the polysilicon gates 50n and 50p are oxidized to grow an oxide film (SiO ₂ ) 32 of 500 to 1500 °.

Next, the contact holes 56 and 58 are opened by removing a part of the oxide film 32 other than the activation regions 12p and 12n,
Next, an oxide film 32 is formed by sputtering titanium (Ti).
Then, after being attached to the entire surface of the P-type and N-type polysilicon gates 50p and 50n exposed in the contact holes 56 and 58, heat treatment is performed at 700 ° C. in a nitrogen atmosphere. Through these processes, titanium silicides 52 and 54, which are first and second metal silicide regions, are formed in these polysilicon portions in contact holes 56 and 58, and a TiN _x film is formed on oxide film 32.

Next, the TiN _X film on the oxide film 32 is removed by etching with sulfuric acid / hydrogen peroxide (sulfuric acid + hydrogen peroxide solution), and the titanium silicide 52 formed in the contact holes 56 and 58 is removed.
And only 54 remain.

Next, a third conductive layer 60 is formed by depositing titanium nitride (TiN) for wiring and patterning the titanium nitride.

By the formation of the third conductive layer 60, the connection structure of the different polarity conductive layers of the first embodiment of the present invention is completed. To complete a CMOS semiconductor device, additional phosphor silicate glass (PSG)
After depositing the film 34, the phosphor silicate glass (PS
G) Heat treatment at 900 ° C. in a nitrogen atmosphere to planarize the film. During this heat treatment, the N-type polysilicon gate (second
The arsenic (As) ions in the conductive layer (50n) diffuse in the third conductive layer 60 and do not move because the third conductive layer 60 has a small diffusion coefficient for arsenic (As). Therefore, no ohmic failure occurs at the interface between the P-type polysilicon gate (first conductive layer) 50p and the titanium silicide 52 as the first metal silicide region.

Next, patterning of a contact hole 38, vapor deposition of aluminum (Al) for wiring, and patterning of the aluminum are performed to form an aluminum electrode 36. Finally, a PSG cover film 40 is deposited, and then patterning of a bonding pad is performed. (Not shown) to complete the CMOS.

Next, a description will be given of a second embodiment of the connection structure of the different polarity conductive layers according to the present invention.

FIGS. 3 (A) and (B) are the corresponding views of FIGS. 1 (A) and (B), respectively. Therefore, in FIGS. 3 (A) and (B), FIG. 1 (A) Components having the same functions as the components shown in (B) and (B) are not described unless otherwise specified. In FIG. 3A, only the main parts are taken out and emphasized.

In the second embodiment, the polysilicon layers forming the first and second conductive layers 70p and 70n are formed as separate areas from each other, and ions for determining the conductivity type are implanted into these polysilicon layers. Have been. And
The P-type polysilicon layer 70p, which is the first conductive layer, is
Forming a polysilicon gate of the OS transistor T _P, a second
A conductive layer N type polysilicon layer 70n is formed a polysilicon gate of the N-channel MOS transistor T _N, the ends of both polysilicon gates 70p and 70n are field oxide film
It has a structure facing away from above on 26. Mainly, a first metal silicide region 72 and a second metal silicide region 74 are provided at opposite ends of the polysilicon gates 70p and 70n, respectively.
The second conductive silicide regions 72 and 74 are buried and electrically connected to each other by increasing the third conductive layer 76 to connect the different polarity conductive layers of the second embodiment of the present invention. The structure is formed. Also in the case of this embodiment, the first and second conductive layers 70p and 70n, the first and second
The metal silicide regions 72 and 74 and the third conductive layer 76 are
It can be formed using the same material as that of the embodiment.

Next, the method of forming the connection structure of the second embodiment will be briefly described. However, since the steps are almost the same as those of the first embodiment, the process steps are different from those of the structure of the first embodiment. Will be mainly described.

When growing a polysilicon film on the gate oxide film 24 and the field oxide film 26 and patterning it,
In the respective gate regions of the MOS transistors _TP and _Tn , they are formed as individual polysilicon film regions so that their respective ends are separated and opposed on the field oxide film. Thereafter, processes similar to those in the first embodiment are sequentially performed to form N-type and P-type polysilicon gates 70n and 70p, and an oxide film 32 is further grown. next,
Of the region of this oxide film 32, both polysilicon gates 70n
And the portions between the opposite ends of the polysilicon gates 70n and 70p, and the portions on the opposite ends of the polysilicon gates 70n and 70p, respectively, are removed, and the portion of the field oxide film 26 between these ends and the polysilicon gates 70n and 70p are removed. Are exposed.

Next, an oxide film 32 is formed by sputtering titanium (Ti).
Upper and polysilicon gates (first and second conductive layers)
After the entire surface is deposited on 70p and 70n, 70
Heat treatment at 0 ° C., both polysilicon gate 70p and
At the end of 70n, titanium silicide regions 72 and 74 to be the first and second metal silicide regions are formed. This heat treatment forms a TiN _X film of titanium on the oxide film 32.

Next, using a suitable mask, etching is performed with sulfuric acid / hydrogen peroxide (sulfuric acid + hydrogen peroxide solution) to remove only the TiN _X film portion formed on the oxide film 32 and the field oxide film 26, thereby forming the film. The remaining titanium silicide regions 72 and 74 are left.

Next, the third conductive layer 76 of titanium nitride is formed by sequentially performing the same processing as in the first embodiment, and the connection structure of the different polarity conductive layers of the second embodiment is completed.

Thereafter, the step of completing the CMOS semiconductor device may be performed in the same manner as the step described in the first embodiment.

Also in this case, after forming the connection structure of the opposite polarity conductive layer, PS
Although heat treatment at a temperature of about 900 ° C. is performed for planarizing the G film 34, the third conductive layer 76 is included in the polysilicon gates 70p and 70n that are the first or second conductive layers. Since the diffusion coefficient for the impurities is small, for example, arsenic (As) ions do not diffuse from the polysilicon gate 70n to the titanium nitride (TiN) film of the third conductive layer. Therefore, there is no possibility that the interface between the polysilicon gate 70p and titanium silicide as the first metal silicide region will cause an ohmic defect.

The present invention is not limited to only the above-described embodiments, and many modifications or changes can be made within the scope of the present invention. For example, in any of the embodiments described above,
As the conductive layers having different polarities, the polysilicon gates of the N and P channel transistors of the CMOS semiconductor device have been described as an example. However, the present invention is not limited to this. For example, a CMOS SRAM (static ram) or the like may be used.
The present invention can be applied to connection between diffusion layers p ⁺ and n ⁺ of PMOS and NMOS, and connection between gate polysilicon and p ⁺ and n ⁺ .

(Effects of the Invention) As is clear from the above description, according to the connection structure of the different polarity conductive layers of the present invention, a metal for ohmic contact is formed on a part of each of the first and second conductive layers of polysilicon. A silicide region is provided, and the first and second conductive layers are electrically connected between the respective metal silicide regions using a third conductive layer having a small diffusion coefficient with respect to an impurity which determines the conductivity type contained in both of the conductive layers. Since the active coupling is performed, the impurities in the first and second conductive layers are prevented from moving through the third conductive layer to the other conductive layer by diffusion. Therefore, no ohmic failure occurs at the interface between polysilicon and silicide due to diffusion of impurities.

When the embodiment of the connection structure of the present invention in which the first and second conductive layers are separately formed is applied to the gate electrode of a CMOS semiconductor device, the first and second metal silicide regions basically ,
It is only necessary to form the first and second conductive layers on the end faces of the opposing ends of the polysilicon, so that the area required for connection can be minimized, and therefore, an extra contact area is required on the field oxide film. And not. Therefore, high integration of the CMOS semiconductor device can be achieved.

In addition to this, since the third conductive layer serving as a pad portion for making contact with the aluminum electrode usually uses a high melting point metal or a high melting point metal compound, it does not affect the lower active region and the field region. In addition, extra contacts can be sufficiently secured. Therefore, the alignment accuracy can be reduced, and the yield can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a cross-sectional view taken along line AA of a main part of a CMOS semiconductor device for explaining one embodiment of a connection structure of different polarity conductive layers according to the present invention. FIGS. 3A and 3B are a plan view and a cross-sectional view taken along line II-II of a main part of a CMOS semiconductor device for explaining a conventional connection structure of different polarity conductive layers. FIGS. FIG. 9 is a cross-sectional view of a main part of a CMOS semiconductor device and a cross-sectional view taken along line BB of the CMOS semiconductor device according to another embodiment of the connection structure of the different polarity conductive layers of the present invention. 12p, 12n: activated region, 20: N-type substrate, 22: P well 24: gate oxide film, 26: field oxide film 30p, 30n: channel cut diffusion layer 32: oxide film, 34 , 40 PSG film 36 Aluminum electrode 38, 42, 56, 58 Contact hole 50p, 70p First conductive layer (P-type polysilicon gate) 50n, 70n Second conductive layer (N-type) .., First metal silicide regions 54, 74... Second metal silicide regions 60, 76... Third conductive layer.

Continued on the front page (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/768 H01L 21/8238 H01L 27/092

Claims (7)

(57) [Claims] 1. A connection structure of a first conductive layer and a second conductive layer made of polysilicon having different conductivity types, wherein: a first metal silicide region provided in a part of the first conductive layer; A second metal silicide region provided in a non-contact state with the first metal silicide region; and a coupling between the first and second metal silicide regions, and determining a conductivity type of the first or second conductive layer. And a third conductive layer having a small diffusion coefficient with respect to the impurity. 2. The connection structure of a different polarity conductive layer according to claim 1, wherein the first and second conductive layers are formed as a common polysilicon layer.
A connection structure for conductive layers having different polarities, which is formed as an adjacent region formed by injecting impurities for determining the conductivity type. 3. The connection structure of different polarity conductive layers according to claim 1, wherein said first and second conductive layers are regions of a polysilicon layer which are separate from each other, and these regions determine a conductivity type. A connection structure for the different polarity conductive layers, each of which is formed as a region into which ions are implanted. 4. The connection structure of a different polarity conductive layer according to claim 2, wherein the bonding between the first and second metal silicide regions and the third conductive layer is performed via a contact hole provided in an insulating layer. A connection structure for a different polarity conductive layer. 5. The connection structure of a different polarity conductive layer according to claim 1, wherein the third conductive layer is formed of TiN, ZrN, TiB ₂ , ZrB ₂ , TiC and Z.
A connection structure for a heteropolar conductive layer, comprising one or more kinds of high melting point metal compounds selected from the group of rC high melting point metal compounds. 6. The connection structure for a heteropolar conductive layer according to claim 1, wherein the first and second metal silicide regions are one type selected from the group consisting of titanium silicide, zirconium silicide, and hafnium silicide. A connection structure of a different polarity conductive layer, which is a region made of a metal silicide. 7. The heteropolar conductive layer connection structure according to claim 1, wherein the impurity determining the conductivity type is an As ion in the case of an N-type conductivity type. Layer connection structure.