JPS6257397A - Time division channel switch circuit - Google Patents

Abstract

PURPOSE:To recrease the number of elements of buffer memories and signal lines by storing the inputted data and an exchanging signal in a memory means every allocated time slot, and allocating the stored data and the exchanging signal to a desired time slot by a selecting means. CONSTITUTION:An input data signal and an exchanging input signal are multiplexed on the same signal line, a DATA and a SIG are allocated on the same time slot, a 2n multiplexed data signal is written in a buffer memory 10 based on a designation of a signal 4 from a writing address control circuit 30. The read information is fed to an address memory circuit 40 through a signal 6 according to the designation of a control circuit 50 and the designated address information is read, a signal 5 is transmitted, the information designated by the signal 5 is read as a data signal 2, according to a selecting address designated by the signal 5, the information of the signal 2 is selected by a selecting circuit 20 and fed as the 2n multiplexed data signal 3 to perform an exchange of the information of the time slot.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time-division call path switch circuit used in a time-division call exchange.

〔overview〕

The present invention provides a time-division channel switching circuit that changes time slots to which data and exchange signals are assigned, in which data assigned to the same time slot and exchange signals corresponding to this data are combined into a desired set. By allocating 1 to each time slot, the number of signal lines and the number of storage elements of the storage means can be reduced.

[Conventional technology]

A time-division multiplexed data line accommodated in a conventional time-division communication path switch circuit carries data represented by digitized voice, data, and image information, as well as monitoring signals and selection signals for this data. They were separated into separate signals for each exchange.

FIG. 3 is a block configuration diagram showing the configuration of a conventional example circuit, in which reference numeral 1a indicates a plurality of n-multiplexed data signals such as a plurality of audio signals, reference numeral 1b indicates a plurality of n-multiplexed exchange signals, and reference numeral 11 indicates a plurality of data signals such as multiplexed voices. A buffer memory 12 stores information on the signal 1a, a buffer memory 12 stores information on the signal 1b, 2a and 2b a plurality of output data and exchange signals read from puff notes January 1 and 12, respectively, 21 and 22 are selection circuits that sequentially select and multiplex signals 2a and 2b, and 35 is a buffer memory 11.
and writing the information of signals 1a and 1b to 12! a write address control circuit that specifies a write address;
Sign 45 indicates signal 2 for buffer memory 11 and work 2.
an address memory circuit 55 for storing information on the address for reading information on a and 2b and the address for selecting the signals 2a and 2b for the selection circuits 21 and 22;
Reference numeral 4 indicates a control circuit for controlling reading and writing of address information to the address memory circuit 45, reference numeral 4 indicates a write control signal and address signal for the buffer memories 11 and 12, and reference numeral 5 indicates a control circuit for controlling reading and writing of address information to the address memory circuit 45;
Read control and read address signals and selection control and selection address signals for the selection circuits 21 and 22; reference numeral 6 indicates respective signals of read and write control, write data information, and write and read addresses for the address memory circuit 45; reference numeral 3a and and 3b indicates n multiplexed data signal lines and exchange signal lines from the selection circuits 21 and 22, respectively.

FIG. 4 is a diagram showing one time slot each of the signal lines 1a, 1b, 3a, and 3b in FIG.
O~DATA (n-1) is n multiplexed data, S
IG O-5IG (n-1) represents n multiplexed switching signals, and TSO to TS (n-1) each represent n time slots.

In this conventional circuit, n-multiplexed information is sequentially written into buffer memories 11 and 12, respectively, by designation of signal 4 from write address control circuit 35. The written information is read out from buffer memories 11 and 12 as signals 2a and 2b in accordance with signal 5 which is read out from address memory circuit 45 in accordance with the designation of signal 6 from control circuit 55. This read information is further transmitted to signal 5.
Signals 3a and 3b are sequentially sent out by selection circuits 21 and 22 designated by , and time slot information of information on signals 1a and 1b is exchanged. Signals 3a and 3b in Fig. 4 are the output TSI and TS2 DATA.
I.

This indicates that SIG 1 and SIG 2 are being exchanged to DAT82.

[Problem that the invention seeks to solve]

In such a conventional time-division communication path switch circuit, the time-division multiplexed data lines accommodated are separated into those for data information and for exchange signals, so a buffer memory is required for each, and the number of memory elements is reduced. There is a drawback that the number of data lines to be accommodated is increased and two data lines are paired, resulting in an increase in the number of signal lines.

SUMMARY OF THE INVENTION The present invention aims to eliminate these drawbacks, and aims to provide a time-division channel switching circuit with a relatively small number of buffer memory elements and signal lines.

[Means for solving problems]

The present invention provides a time-division channel switch circuit comprising a storage means for temporarily storing data and an exchange signal assigned to a time slot, and a selection means for assigning the data and exchange signal to a desired time slot. is provided with a terminal for inputting data assigned to the same time slot and a replacement signal corresponding to the data, and the storage means stores the data and replacement signal input to the terminal in the time slot to which it is assigned. The selection means is characterized in that it is configured to allocate the data and exchange signal stored in the storage means to a desired time slot.

[Effect]

The incoming data and the exchange signal corresponding to this data are paired and attached to the same time slot v1. This pair of information is temporarily stored in the storage means for each time slot. The pair of information read from the storage means is assigned to a desired time slot by the selection means and output.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block configuration diagram showing the configuration of a circuit according to an embodiment of the present invention.

First, the configuration of this embodiment circuit will be explained based on FIG. This embodiment circuit includes a buffer memory 10 that stores information on a plurality of data signals 1 in which an input data signal and an exchange input signal are multiplexed 2n on the same signal line, and a plurality of data signals read from the buffer memory 10. a selection circuit 20 that sequentially selects 2, multiplexes 2n, and outputs data signal 3;
, a write address control circuit 30 that outputs a signal 4 for writing data signal 1 to the buffer memory 10 and specifying a write address; and an address and selection circuit 20 for reading information of data signal 2 from the buffer memory 10.
The address memory circuit 40 stores the information of the signal 5 related to the selection of the data signal 2 for the address memory circuit 40, and the control circuit 50 outputs the signal 6 for controlling reading and writing of address information to the address memory circuit 40.

Next, the operation of this embodiment circuit will be explained based on FIGS. 1 and 2.

The input data signal and the replacement input signal are multiplexed on the same signal line, and the DATA and SI signals are multiplexed on the same signal line.
As the data signal 1 to which G is assigned and 2n multiplexed, the write address control circuit 3 sends the data signal 1 to the buffer memory 10.
It is written based on the designation of signal 4 from 0. The read information is designated by the control circuit 50 through the signal 6 to the address memory circuit 40 in the same manner as the conventional method, and the address memory circuit 40 reads out the information of the designated address and sends out the signal 5. The information at the address designated by the signal 5 is read out as the data signal 2, and the information at the signal 2 is selected by the selection circuit 20 according to the selection address designated by the signal 5, and is sent out as the 2n multiplexed data signal 3. , time slot information is exchanged.

〔Effect of the invention〕

As explained above, the present invention enables data signals represented by multiplexed voice, data, and images manually input to a time-sharing call switch and exchange signals represented by monitoring signals and selection signals to be the same. Since it is time-division multiplexed on the signal line, the human output signal line of the time-division call switch is reduced to 1/2,
In addition, the number of elements in the buffer memory for the time division call switch is reduced to 1.
It has the effect of increasing the number to 72.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 shows time slots for each part of the signals in FIG. 1. FIG. 3 is a block configuration diagram showing the configuration of a conventional circuit. FIG. 4 is a time slot allocation diagram for each part of the signals in FIG. 3. 10.11.12...Buffer memory, 20.21.
22... Selection circuit, 30.35... Write address control circuit, 40.45... Address memory circuit, 50
．． 55...control circuit. Patent Applicant: NEC Corporation, □ Agent: Patent Attorney Nao Takashi Ide:, Figure 1: Configuration diagram of the embodiment M 1 Figure Time slot allocation diagram of the embodiment 32 Figure Configuration of the conventional example ° Figure M 3 Circle

Claims (1)

[Claims] (1) In a time-division channel switch circuit comprising a storage means for temporarily storing data and an exchange signal assigned to a time slot, and a selection means for assigning the data and exchange signal to a desired time slot. , a terminal for inputting data assigned to the same time slot and a replacement signal corresponding to this data, and the storage means stores the data input to the terminal and the replacement signal for each time slot to which it is assigned. 2. A time-division channel switching circuit, wherein the selection means is configured to allocate the data and exchange signal stored in the storage means to a desired time slot.