JPS6033796A - Memory switch control system - Google Patents

Abstract

PURPOSE:To utilize efficiently a channel memory by applying write and read control of a line data depending on the content of information read from an address control storage memory storage area of a buffer memory. CONSTITUTION:A channel switch 34 is split into three memory areas 34A, 34B and 34C; for data write control information on an incoming multiplex transmission line 11, data read control information to an outgoing multiplex transmission line 12 and data Di, Dj for incoming multiplex transmission line. When a time slot counter 31 represents a ti address and write control information alpha is read, the data Di carried in the time slot ti on the incoming multiplex line 11 is stored in the address alpha of the channel switch 34. On the other hand, when the time slot counter 32 represents tj address and the read control information alpha are read, the data Di of the incoming multiplex transmission line stored in the address alpha of the channel switch 34 is read to the outgoing multiplex transmission line 12 by using the time slot Dj.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a memory switch control system, and in particular to a data buffer memory for temporarily storing line data and an address control memory for holding an address for accessing the data buffer memory. This invention relates to a switching control system in a time division exchange having a one-stage time switch for converting time slots.

[Prior art]

FIG. 1 is a diagram showing a conventional switch control method.

For example, a multiplex transmission line with a speed of 1.544 Mb/s is used as a transmission line, and a data buffer memory for storing data signals sent from subscribers and addresses on this data buffer memory are accessed. A time slot conversion memory for shifting the data signal on the input multiplex transmission path to an arbitrary time position on the output multiplex transmission path is provided corresponding to the time slot, and terminal data D1 sent at time slot number t□ is provided. This shows the case where data signals RI and RI, which are sent from the terminal at time slot i and tj, are exchanged. In FIG. 1, 11 is an input multiplex transmission line, 12 is an output multiplex transmission line, 13 is a data buffer memory that stores data signals sent from subscribers for a certain period of time, 14 is a time slot counter, and 15 is a data buffer memory. 1
3 is a holding memory for performing time slot conversion, and 16 is a selector for selecting the output of either the time slot counter 14 or the time slot conversion holding memory 15. Note that the time slot conversion holding memory 15 is sequentially and periodically accessed by the same click source as the time slot counter 14. Reference numeral 17 denotes a communication path switch for performing switching.

The data signals on the input multiplex transmission line 11 and the output multiplex transmission line 12 are time-division multiplexed into N time slots,
The address of the data buffer memory 13 is associated with each of these N time slot numbers. The signals stored in the data buffer memory 13 can be read out at any time according to the designated address stored in the time slot conversion holding memory 15, and write operations are performed periodically according to the output of the time slot counter 14. . For this reason, the address access time of the data buffer memory 3 is divided into 27 periods of write time and read time.

Next, the operation of this conventional example will be explained using the time chart of FIG. Figure 2 (a) shows the input multiplex transmission path, Figure 2 (b) (o) shows the data buffer memory, Figure 2 (,1
) is the outgoing multiplex transmission path. By writing tj at address t and t at address tj of the 3fl holding memory 5, the data signal D□ of the input multiplex transmission line 11 is written to address ti of the data buffer memory, and reading is performed as follows.
The output multiplex transmission path 1 is carried out at time slot number t, .
2 is sent out. As a result of this operation, terminal B receives the transmission signal D□ from terminal A, which is sent at time slot number t□.

On the other hand, the data signal Dj on the input multiplex transmission path l sent from terminal B to terminal A is stored in the data buffer memory tj@
The readout is performed using the time slot number t□
The signal is sent to the outgoing multiplex transmission path 12 and received by the terminal A. Through this series of operations, data signals between terminal A and terminal B are exchanged.

The following describes the exchange operation when communicating between low-speed terminals that uses only one time slot in one data frame to send and receive one data signal. However, a high-speed exchange operation 1 between terminals using a plurality of times Ell'/) within one data frame can be similarly explained.

The conventional method described above has the following three drawbacks. The first is the time slot conversion holding memory 15.
By making the data buffer memory 13 and data buffer memory 13 separate functional blocks, peripheral interface hardware,
Increase in interface line power. Second, since the addresses of the time slot conversion holding memory 15 and the data buffer memory 13 are assigned to correspond to the time slots on the input multiplex transmission path 11, all the time slots on the multiplex transmission path cannot be stored. It is necessary to always prepare the necessary amount of buffer memory. That is, this buffer memory 15
This means that only the number of simultaneous connections (call handling) can actually be used, and the memory is not used effectively.

Third, the input multiplex transmission path 111.0 data signals are not all circuit-switched signals, but packet-switched signals are mixed, and when a call is set up, each terminal uses circuit-switched or packet-switched signals. It cannot be adapted to a communication form in which exchange can be optionally selected.

[Purpose of the invention]

It is an object of the present invention to eliminate the above-mentioned conventional drawbacks, to make it possible to efficiently utilize IL1 channel memory, to simplify the hardware configuration, and to enable a new communication type, that is, line switching or packet switching, to be implemented as desired. It is an object of the present invention to provide a memory switch control method that can be applied to selectable forms.

[Summary of the invention]

The memory switch control method of the present invention converts time slots using a data buffer memory that temporarily stores line data and an address control holding memory that holds an address for accessing the data buffer memory.
In a time division interchange IF% equipped with a step time switch, a buffer memory is provided which integrates the holding memory and the buffer memory, and the buffer memory is divided into an address control holding memory storage area and a line data storage buffer area. However, the information content for write control and bladder evacuation control read from the address control holding memory storage area is characterized in that it performs write and read control of line data.

[Embodiments of the invention]

FIG. 3 is a diagram showing the basic principle of the present invention.

In FIG. 3, 31 is a time slot counter that operates in synchronization with the phase of the data signal on the input multiplex transmission line ll;
32 is a time slot counter that operates in synchronization with the phase of the data signal on the output multiplex transmission line 12; 34 is a channel switch that can realize time slot conversion within a unified buffer; A selector circuit for switching between read information (for controlling writing of data on the input multiplex transmission line 11 and for controlling reading of data on the output multiplex transmission line 12) and the instruction tfl information of the time slot counters 31 and 32. be. The operating principle of the present invention will be explained below by taking the conversion of time slot )1□Ht as an example.

First, the write operation will be explained. Input multiplex transmission line 11
The data signal D□ carried in the upper time slot t□ is
Immediately before arriving at the jjjQ path switch 34, the time slot counter 31, which is incremented in synchronization with the phase of the input multiplex transmission path 11, indicates the t□ address, and this information is selected by the selector 33. Call path switch 34 is accessed. The communication path switch 34 controls information for writing data on the input multiplex transmission path 11 and the output multiplex transmission path 12.
3 memory areas 34A for storing input multiplex transmission line data Di and Dj;
, 34B, and 34C, and when address t1 is accessed, write control information α is read out, and by performing switching control so that this information α is selected by the selector 33, the communication path switch 34 Data D1 carried in time slot t□ is stored at address α.

Next, the read operation will be explained. Output multiplex transmission line 12
When the time slot counter 32, which operates in synchronization with the clock phase of , indicates address tj, and the selector 33 is switched to access the information for reading U1 (feeding),
The readout control information α at address tj of the communication path switch 34 is read out. By performing switching control so that this information α is selected by the selector 33, the communication path switch 3
Data D□ of input multiplex transmission line stored at address α of 4
is read out onto the outgoing multiplex M12 using time slot tj.

Through the above series of operations, time slot conversion from % ti to tj is performed. Similarly, time slot conversion from tj to t1 can be performed, and through the above series of operations, it is possible to realize communication path control to enable bidirectional communication between t□ and tj. As is clear from the above explanation, these operations are performed using easy C one-way communication control (t□→
tj or t.

→t□ (when only one side of the time slot conversion is performed).

FIG. 4 shows an example of the operation cycle of the communication path switch 34. The A cycle is a cycle in which write control Ln information is read based on the counter Ti1 information of the time slot counter 31, and the C cycle is a cycle in which the input multiplex transmission line data 11 is transferred to the communication path switch 34 based on this read information.
The cycle for writing to the data buffer area 34B in
The cycle is a cycle in which readout control information is read out based on the counter information of the time slot counter 32, and the D cycle is a cycle in which readout control information is read out based on the information read out in the B cycle. The cycle E cycle is a soft cycle for reading out the data signal stored in the data buffer section 34B in the data buffer section 34B. This is a cycle for writing or reading data (used for storing control information).

FIG. 5 shows the application of the principle of the present invention to a parallel switching system. For example, the speed of the input multiplex transmission line 11 is
128 M b/s, and the data signal sent from the terminal is assumed to be octet multiplexed into 8 bits. 51 is a circuit that stores 04 bits of this octet multiplexed data over 8 data frames and performs serial-parallel conversion as 64-bit parallel data;
is a circuit for converting 04-bit parallel data to the original serial octet multiplex data. Like this 6
By performing 4-bit serial-to-parallel conversion, b/s
= 2 Mb/e and time slot conversion within the channel switch 34. When the communication path switch 34 operates according to the operation cycle shown in FIG. 4, the cycle time of the memory used in the communication path switch 34 is as follows. Note that the communication path switch 34 is used for readout control,
The number of bits required for each address in the holding memory units 34A and 34C for write control is 2 x ((lo
g, n )X bits), the number of required addresses is n words. However, let (()) be defined as follows.

([ ] indicates a Gauss symbol) FIG. 6 shows an embodiment of a method for allocating addresses in a communication path switch when the present invention is used as a line concentration switch.

Figure 6 shows t, mt, (bidirectional communication), 'to''
'J48 (two-way communication), t, →t□. . (Two-way communication), T engineering → 1. The method for allocating data buffers in the case of time slot conversion (one-way communication) is shown below. In this example, when the time slot multiplicity (the number of time slots in one data frame) on the multiplex transmission path is 1024, the use area is secured in order from the oldest number.

One of the write and read control areas 34A and 34C is
Randomly assigned during call setup.

If only such communication is being performed at a certain point in time, the area corresponding to addresses 1 and 1 of the data buffer section 34B at this point is in an unused state of 0 1016 (indicated by diagonal lines). ), it can be used immobile for other purposes.

The method of allocating the data buffer area 34B will be described in further detail below. FIG. 7(a) shows an example of the structure of the management table when the data buffer area 34B shown in FIG. 6 is divided into units of 32 bytes (-256 bits) to create 256 modules. .Each module 71 has 3!! on the buffer area in FIG.
Consists of consecutive blocks. Also, Fig. 7(b)
As shown in the figure, a management table 72 is prepared for each module that shows which blocks are currently in use, and when only 1 block, 2 blocks, 3 blocks, or 4 blocks are used in each module, The codes in the left half of the management table are tlool and 010.011, respectively.
, 100. Note that if no l block is used, it is coded as 000, and this buffer area is used for other purposes on the buffer memory, as will be described later.

In the right half of the management table, the buffer area allocation corresponds to the method and l to l, and stores °゛1゛' when in use and °°O'' when not in use. , shows the case where there are 1024 time slots on the multiplex transmission path, and it is possible to allocate a 64-bit wide buffer area for each time slot, and the usage/unuse status of the buffer area in units of 04 bits is shown below. It corresponds to the right part in the management table.

Since one module is configured for every four time slots, the management table has 256 entry addresses.

FIG. 8 shows an algorithm for allocating buffer areas when a search request for an empty buffer area is input from the exchange control system at the time of call setup using the above-mentioned management table.

It is checked whether there is a request to search for a free buffer area from the exchange control system, and if there is no request, the presence or absence of a request is checked repeatedly until there is a request to release the used buffer area (steps 81 and 87). If there is a request to release the buffer area, the code in the management table 72 is subtracted by -l and the table 72 is updated (step aa, (A)).
. Additionally, when there is a request to search for a free buffer area, all codes for each module in the management table 72 are 00.
00'''' allocates the buffer area at the lowest address in any module (steps 82 and 89).When the code for each module is 011'', 3 blocks out of the raw blocks are used. Therefore, the remaining free blocks are allocated (step 83.90). When the hood of each module has "010" or the code of each module has "001", only 2 or 1 block in the cow block is used, so the lowest number in any module is used. Allocate unused buffer area (steps 84゜85+91)
. When the allocation is completed, the code of the corresponding module is incremented by +1 and the usage/unusage status table is updated (step 92).

In addition, if all of steps 82 to 85 are NOO,
Since the entire buffer is used, a busy display is performed (step 86).

FIG. 9 is a diagram showing, as another embodiment of the present invention, a method of using a communication path switch when circuit-switched data and packet-switched data are mixed and multiplexed on a multiplex transmission path. It is. 91 is a control section, and 92 is a main storage section. Reference numeral 34 denotes a communication path switch section, which is composed of a packet switching data buffer section 3+2 and a line switching data buffer section 341.

As mentioned above, the circuit switching data buffer section 341 is empty except for the buffer area required for the number of simultaneous circuit switching connections, so this area can be dynamically used.
It becomes possible to allocate it as a buffer area 342 for packet exchange.

The control unit 91 has the aforementioned management table 72 regarding buffer area allocation, and by using this information, it is possible to effectively utilize the buffer area of the communication path switch 34. Note that some of the packet data accumulated in the communication path switch 34 is mapped to the main storage section 92, and when the packet exchange buffer area 342 becomes empty, it is taken into the communication path switch 34 again and sent to the control section. 91 G,T, a method of performing packet data processing can be considered as an example. Regarding the above-mentioned free buffer area, for example, the free/occupied state is managed in units of 32 bytes (:), the program in the main storage section 92 is mapped to the channel switch 34, and the control section 91 It is also possible to use

〔Effect of the invention〕

More than R? As described above, according to the present invention, it is possible to realize a communication channel configuration that integrates the holding memory and the buffer memory in a one-stage time switch, and the hardware configuration is simplified, and the configuration using the LSItJ technique can be realized. becomes easier. In addition, even when packet-switched data signals and circuit-switched data signals coexist on multiplexed transmission paths, it is possible to use channel memory efficiently, making it possible to apply economic effects to new communication formats. It has the advantage of being able to demonstrate

[Brief explanation of drawings]

FIG. 1 is a block diagram of a communication path for a memory switch type time-division switch using conventional technology, FIG. 2 is a time chart of FIG. 1, and FIG. 3 is a block diagram of a memory switch type communication path according to the present invention. Yes, Fig. 4 is an operation cycle chart of the communication path switch according to the present invention, Fig. #1\5 is a configuration diagram when the invention is applied to a parallel switching system, and Fig. 6 is a diagram of address assignment in the communication path switch. 7 is a diagram of an example, and FIG. 7 is the configuration of the Q table when allocating addresses in FIG. 6. FIG. The figure is a configuration diagram of an embodiment of an exchange in which the communication path switch according to the present invention is applied to a case where line switching data and packet switching data are mixed and multiplexed transmitted on a multiplex transmission path. 11: Input multiplex transmission line, 12: Output multiplex transmission line, 13 Data buffer memory, 14: Time slot counter, 15
1 holding memory, 16: selector, 17 dual channel switch, 31: time slot count (synchronized with input multiplex transmission line), 32: time slot counter (synchronized with output multiplex transmission line), 33: selector, 34: tff , - communication path switch using a buffer, 51: serial/parallel conversion circuit, 52: parallel/serial conversion circuit, 71: buffer area within the communication path switch, 72; communication path buffer management table, 91: control section, 92 main storage section. ffi-11's Figure 2 Do--1 data frame-) 12 Figure 3 Figure 4

Claims (1)

[Claims] In a time division exchange equipped with a one-stage time switch that converts time slots using a data buffer memory that temporarily stores line data and an address control holding memory that holds addresses for accessing the data buffer memory, A buffer memory is provided in which a memory and the buffer memory are integrated, and the buffer memory is divided into an address control holding memory storage area and a line data storage buffer area, and data read from the address control holding memory storage area is provided. A memory switch control method characterized in that writing and reading of line data is controlled based on information contents for write control and read control.