JPS6370698A - Time-division exchange system - Google Patents

Abstract

PURPOSE:To rearrange a channel in communication without any instantaneous break by providing two read or write control means and switching them to sides where necessary information is set at every request for channel rearrangement. CONSTITUTION:Channel control information sent out of a switch read control circuit 3 is supplied to switch memories 11 and 12 alternately at intervals of one frame with the control signal of a frame signal FCK. Then when communication channels on an incoming-side time-division multiplex highway are rearranged, channel conversion information after channel rearrangement is set in a read control circuit 4 for in-communication channel rearrangement. Here, the circuits 4 and 3 are of the same constitution. The circuit 4 receives a start signal after the setting, but the circuits 3 and 4 are switched right before the head communication information in a frame where channels are rearranged is read out. If a request for rearrangement is made during communication after the rearrangement, channel conversion control information is set in the circuit 3 this time and the same control is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division switching system, and particularly to a switching system that can realize communication channel relocation without momentary interruption.

[Conventional technology]

In time division switching, multiple signals are time division multiplexed onto one common line (highway). This reversal of the multiplexing order is called phase conversion or time slot conversion. Time slot conversion can be realized using a switch memory, but for this purpose it is necessary to control the address for writing into the memory and the address for reading from the memory in accordance with each time slot. Since the address for writing can be given sequentially from 1 to n according to the time slot, address control for writing can be easily realized by using a counter circuit that increments by 1 for each time slot. On the other hand, since the order of read addresses has no relation to the order of time slots, it is necessary to have a correspondence table of read addresses according to time slots.

[Problem that the invention seeks to solve]

As described above, a large number of channels are arranged on a highway in a time-division communication path, but no time-division switching system has been considered in the past that allows channels in communication to be rearranged without momentary interruption. If channels can be rearranged without interruption during one communication, line editing and batch switching of lines for group switching and maintenance management can be easily performed.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and to provide a time division switching system that allows communication to be continued without momentary interruption in a switching device or the like when channels in communication are rearranged as necessary.

[Means to solve the problem]

In order to achieve the above object, the time division exchange method of the present invention is as follows:
A communication channel relocation read or write control means having the same configuration as the read or write control means is provided, and in order to switch the communication channel on the input or output time division multiplex highway to another channel without momentary interruption, the communication channel After setting channel conversion control information after relocation in the communication channel relocation read or write control means, control of the switch memory is controlled from the communication channel relocation read or write control means. The feature is that the functions of the two devices are switched, and thereafter, the two devices are switched each time a channel relocation request is made during communication.

[For production]

In the present invention, when all communication information in the same frame on the ingress time division multiplex highway is exchanged in the same frame on the egress time division multiplex highway, the need for channel relocation during communication is addressed. (Accordingly, the channel conversion control information after channel relocation during communication is read or written for channel relocation) Control circuit F″--Control of the switch memory by the communication channel relocation start signal instructing the setting frame. switch read or write)
(read or write for relocation of the channel in communication) from the control circuit to the control circuit, exchange the functions of both, and thereafter perform the read or write for relocation of the channel in communication for each request for relocation of the channel in communication in the same manner. C or write) control circuit and switch read or write) control circuit are alternately switched, and the switch memory performs channel rearrangement during communication without momentary interruption.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a time division switch showing one embodiment of the present invention. In FIG. 1, 11t12 is a switch memory, 2 is a switch write control circuit, 3 is a switch read control circuit, 4 is a read control circuit for channel relocation during communication, 54+53.54 is a decoder, and 52 is a selector. Communication information in the same frame on the ingress time division multiplex highway is all exchanged within the same frame on the egress time division multiplex highway.The switch memory is double buffered as a time division exchange circuit, and the switch write control circuit 2 is made up of a counter circuit with a sequential 548 function, and the switch readout control circuit 3 is made up of a random access memory having a random read function.

In FIG. 1, one frame of communication information on the incoming time division multiplex highway is alternately written into the switch memory 11 or the switch memory 12 every frame period by a decoder circuit 51. In parallel, the communication information in the switch memory 12 or the switch memory 1 is alternately output to the output time division multiplex highway for each frame IRM by the selector 52. That is, when the switch memory 11 is write-only, the switch memory I2 is read-only.

Hereinafter, the cycle time of the switch memory 11t12 is first a read access time and then a write access time.

In write control, communication information is sequentially written to addresses in the switch memory 11 using sequential addresses output from the switch write control circuit (counter circuit) 2. On the other hand, in the read control, communication information is randomly read from the switch memory 12 using a random address of the switch read control circuit 3.

During a period in which the communication channel on the incoming time division multiplex highway is not rearranged, the switch readout control circuit 3 performs channel conversion between the person and the outgoing time division multiplex highway, for example. The switch readout control circuit 3 is composed of a normal random access memory, and its memory address indicates the channel number on the incoming time division multiplex highway, and the channel conversion control information indicates the channel number on the outgoing time division multiplex highway. .

The channel conversion control information sent from the switch readout control circuit 3 is controlled by the control signal of the frame signal FCK.
(2) The signal is alternately supplied to the switch memories 11 and 12 for each frame.

Next, when relocating communication channels on the incoming time division multiplex highway, channel conversion information after channel relocation is set in the read control circuit 4 for channel relocation during communication. Here, the read control circuit 4 for channel relocation during communication
has the same hardware configuration as the switch readout control circuit 3. Therefore, the address supplied to the channel relocation read control circuit 4 during communication indicates the channel number on the incoming time division multiplex highway, and the control information indicates the channel number on the outgoing time division multiplex highway.

After setting the channel conversion information after channel relocation in the communication channel relocation readout control circuit 4, a communication channel relocation activation signal is received, but the communication channel relocation readout control circuit 4 receives the communication channel relocation activation signal. Control port lol
The switching timing at t4 is just before the first communication information in the frame in which channel relocation has been performed is read out onto the outgoing time division multiplex highway (frame break).
It will be held in However, when controlling the switch memory 11*12 to perform random writing and sequential reading, the first communication information in the frame in which channel relocation has been performed during communication is the memory switch 11+12.
This is done just before it is written to.

Therefore, the frame signal FCK indicating the first channel of the frame in which the communication channel relocation is to be performed and the communication channel relocation start signal are input into the time division switching circuit in synchronization.
Both are switched by the next frame signal FCK, and the functions of both are also switched.

FIG. 2 is a detailed block diagram of the main part S in FIG. 1. In FIG. 2, 6 is a flip-flop circuit 27 and an AND gate, 8 is a switching timing counter circuit,
Other parts represent the same elements as the same reference numerals in FIG.

After the switching is completed by the above-mentioned operation, the flip-flop circuit 6 and the switching timing counter circuit 8 are reset (each output level is set to RO" level). Thereafter, the readout control circuit 4 for channel relocation during communication uses the switch memory. 11 and 12 are performed, but if control is performed again after channel relocation during 1 communication, channel conversion control information is set in the switch readout control circuit 3, and the same control as described above is repeated.In addition, the switching timing counter circuit 8 can be easily realized using a normal binary counter.

In FIG. 2, a switch read control circuit 3 controls switch memories 11 and 12.

Here, when the signal supplied to the decoder circuit 53 is It O' level, the sequential address of the counter circuit 2 is supplied to the switch readout control circuit 3 via the decoder circuit 5 and the selector circuit 58, and the channel conversion control is performed. Information is sent out. The read channel conversion control information is then sent to the decoder circuit 55 via the selector circuit 56.

The decoder circuit 55 is supplied with the frame signal FCK, and signal routes are alternately set to the switch memories 11 and 12 every frame.

When it becomes necessary to relocate the channel during communication, channel conversion control information after relocation of the channel during communication is set in the read control port PII/I for relocation of the channel during communication. At this time, since the output of the flip-flop circuit 6 is at "0" level, the channel conversion I11 control information is transmitted to the decoder circuit 510.
The signal is sent to the readout control circuit 4 for channel relocation during communication. On the other hand, the write address of the read control circuit 4 for relocating channels during communication is supplied to the read control circuit 4 for relocating channels during communication via the selector circuit 57 .

When the channel conversion control information after communication channel relocation is set, the communication channel relocation activation signal is the frame signal FCK of the first frame in which communication channel relocation is performed.
It is input to the time division exchange circuit in synchronization with . That is, the channel relocation activation signal during communication is latched by the flip-flop circuit 6, and the output level becomes 1''. This signal level and the frame signal FCK (assumed to be at "1" level) are input to the AND gate 7. and increases the count value of the switching timing counter circuit 8. Then,
When the next frame signal FCK is input to the switching timing counter circuit 8 and the output level becomes "10", the selector circuits 56, 57, 58, decoder circuits 5a, 51o
A control signal Hi I+ level is supplied to the switch memories 11 and 12 to control the switching memory 11 and 12 for relocating the communication channel before reading out the communication information of the first frame for which the communication channel has been reallocated onto the outgoing time division multiplex highway. It switches to the read control circuit 4. Then, the switch readout control circuit 3
The function is also replaced with the readout control circuit 4 for channel relocation during communication. Therefore, when it becomes necessary to rearrange the channel during communication next time, the channel conversion control information after relocation of the channel during communication is set in the switch memory read control circuit 3, and the same control as described above is performed.

By performing such control, channel relocation during communication can be realized without momentary interruption. An example of this operation will be explained next.

3, 4, and 5 are operational diagrams showing channel relocation control during communication in the time division switching circuit of the present invention. Now, assume that the number of channels in one frame on the outgoing time division multiplex highway is three channels. The relative time position of channels in each frame is called a time slot, and the relative time position of channels 1, 2.3 in a frame is TI,
Indicated by T2°T3 time slots. In frame 1, channel 1, channel 2, and channel 3 are used by nine users x, y, and z, respectively. The communication information in frame i is assumed to be X, ,Y□yZi. User communication information X, Y, and Z are channel-converted by switch memories 11+12, and user communication information of V is sent to channel 1 on the outgoing time division multiplex highway, 2 to channel 2, and X to channel 3. .

Frame 2 is a frame in which channels are rearranged during 5 communications, and channels 1. In this example, channels 2 and 3 are used by users Z, X, and Y, respectively.

Switch memory 11. The switch memory 12 is a memory that stores communication information for three channels, Ax, A2.
, A3 indicate memory addresses.

Switch readout control circuit 3. The communication channel relocation read control circuit 4 is a control memory that performs channel conversion for three channels.

FIG. 3 shows the channel conversion operation at one point in T3 time slot 1 of frame 1 on the outgoing time division multiplex highway, and FIG. 4 shows the T3 time slot in frame 2 after channel relocation during communication. Figure 5 shows frame 3 after channel relocation during communication.
The time slot T3 is shown in FIG.

Furthermore, even if channel relocation is performed during communication on the ingress time division multiplex highway, it is assumed that channel relocation is not performed in frames on the egress time division multiplex highway.

In addition, when performing communication channel relocation on the outgoing time division multiplex highway, by changing only the channel conversion control information set in the switch readout control circuit 3 and the communication channel relocation readout control circuit 4, It can be easily achieved.

First, in FIG. 3, communication information XO of frame 0 already written in the switch memory 12 is read from address A1 (read cycle) and stored in T3 of frame 1 on the outgoing time division multiplex highway. . Next, information z1 of the third channel of frame 1 on the incoming time division multiplex highway is written to address A3 of switch memory 1 (write cycle). When reading from the switch memory 12, the sequential address A3 sent from the counter circuit 2 is read from the decoder circuit 58 and the selector circuit 5.
The address A3 of the switch readout control circuit 3 is accessed via the address A3, and the channel conversion control information A1 is read out. This control information is then transmitted to the selector circuit 56.
The address A1 of the switch memory 12 is accessed via the decoder circuit 55. On the other hand, switch memory 11
In the writing control, the read address A3 sent from the counter circuit 2 writes communication information z1 to the address A3 of the switch memory 11 via the decoder circuit 54.

Channel conversion control information after channel change is previously set in the communication channel relocation read control circuit 4 in order to relocate the communication channel from frame 2 of the incoming time division multiplex highway.

Since it is assumed that channel relocation is not performed on the outgoing time division multiplex highway, address A of the read control circuit 4 for channel relocation during communication.

, the switch memory address A3+address A2 is set to the switch memory address A1+the switch memory address A2 is set to the address A3.

When channel relocation is requested during communication, the relocation is controlled in this order.

In FIG. 4, the communication information of frame 2 in which channel relocation was performed during communication is written to the switch memory 12 (
(write cycle), communication information of frame 1 on the incoming time division multiplex highway is read from the switch memory 1 (read cycle).

In this case, frame 1 on the ingress time-division multiplex highway is written to the switch memory 11 with its original arrangement, but the next frame 2 requires channel relocation, so frame 2 is switched. When writing to the memory 12, it must be controlled by the read control circuit 4 for channel relocation during communication. That is, the switch readout control circuit 3 controls the communication information X1 is read from the switch memory 1 until the communication information X1 is read out. 5. Switch memory channel conversion control to the channel relocation read control circuit 4 during communication. Therefore, in FIG. 4, since the switching has not yet been performed, the information Y2 of T3 of frame 2 on the ingress time division multiplex highway is switched from the sequential address A3 sent from the counter circuit 2 via the decoder circuit 54. It is written by accessing address A3 of memory 12. Next, the address A3 sent from the counter circuit 2 is sent to the decoder circuit 5 and the selector circuit 5.
When the address A3 of the switch readout control circuit 3 is accessed via the switch readout control circuit 3 and the channel conversion control information A is read out, this channel conversion control information is transferred to the selector circuit 5.
6. By accessing the address A of the switch memory 11 via the decoder circuit 55, the communication information
is read out and stored in T3 of frame 2 on the outgoing time division multiplex highway.

In FIG. 5, the communication information of frame 3 on the ingress time division multiplex highway is written to the switch memory 11,
In parallel with this, the readout control circuit 4 for channel relocation during communication reads communication information from the switch memory 12. That is, since the selector 5 is switched from 5 to 57 by the channel relocation activation signal during communication, the communication information V3 of 73 of frame 3 on the incoming time division multiplex highway is sequentially sent from the counter circuit 2. Address A3 is written here by accessing address A3 of switch memory 11 via decoder circuit 54. Next, address A from counter circuit 2
3 is the decoder circuit 5, and address A of the read control circuit 4 for channel relocation during communication via the selector circuit 57.
3 and the channel conversion control information A2 is read, this control information A2 is transferred to the selector circuit 56.
, accesses address A2 of switch memory 12 via decoder circuit 55, reads communication information X2, and stores it in T3 of frame 3 on the outgoing time division multiplex highway.

After this, when communication channel relocation is requested again, the communication channel relocation readout control circuit switches from 4 to 3, and from then on, both become the communication channel relocation readout control circuits. .

This operation makes it possible to reallocate channels during communication without momentary interruption.

In addition, in this embodiment, even if the write control of the switch memory is performed by sequential write and the read control is performed by random read, the same implementation can be achieved.

Furthermore, if the time division switching circuit performs all switching within the same frame on the ingress time division multiplex highway, the configuration method and method III# of the present invention can be executed even if the switch memory is not a double buffer system. By doing so, it is possible to reallocate channels during communication without any interruption.

〔Effect of the invention〕

As described above, according to the present invention, channel allocation during communication can be performed without momentary interruption, and therefore line editing and batch switching of lines for group switching and maintenance management can be realized. Further, applications such as channel switching during communication in mobile communication are also possible.

[Brief explanation of the drawing]

Fig. 1 is a functional block diagram of a time division switching system showing an embodiment of the present invention, Fig. 2 is a detailed block diagram of the main parts in Fig. 1, and Figs. FIG. 3 is an explanatory diagram of channel relocation operation during communication according to the invention. 12.12: Switch memory, 2: Switch write control circuit (counter), 3: Switch read control circuit,
4: Read control circuit for channel relocation during communication, 5□,
53-55+ 59+ 5to: Decoder circuit, 52
．． 58-5 days = selector circuit, 6: flip-prop circuit, 7: AND game 1., 8: switching timing counter circuit.

Claims (1)

[Claims] (1) It has a switch memory that stores communication information on the ingress time division multiplex highway, a write control means that controls writing to the switch memory, and a read control means that controls reading of the switch memory, Channel conversion control information of the switch memory is stored in the reading or writing control means, and all communication information within the same frame on the ingress time division multiplex highway is exchanged within the same frame on the egress time division multiplex highway. In the time division switching system, a read or write control means for relocating channels during communication having the same configuration as the read or write control means is provided, and the communication channel on the input or output time division multiplex highway can be transferred to another channel without interruption. In order to switch, the channel conversion control information after relocation of the communication channel is set in the communication channel relocation read or write control means, and then the control of the switch memory is transferred from the switch read or write control means to the communication channel relocation. A time division exchange method characterized by switching to a read or write control means for placement, exchanging the functions of both, and thereafter switching between the two means for each request for channel relocation during communication.